USB3.2 Gen2 Single Lane Re-Timer IP Core
Secure Boot SDK based on NIST CAVP validated cryptographic algorithms and standards
MIPI C-PHY/D-PHY Combo IP CSI-2 TX
90nm FTP Non Volatile Memory for Standard CMOS Logic Process
QOI Image Compression IP Cores available from CAST and Ocean Logic
Imagination Joins Baidu PaddlePaddle "Hardware Ecosystem Co-Creation Program"
Arasan announces its 2'nd Generation of CAN IP
An 800 Mpixels/s, ~260 LUTs Implementation of the QOI Lossless Image Compression Algorithm and its Improvement through Hilbert Scanning
New Ethernet Adaptation Layer Adds Control Option to MIPI A-PHY Automotive Networks
AES 256 algorithm towards Data Security in Edge Computing Environment
Rambus CSI-2 Tx Controller Core is ISO-26262 Certified
Optimized on-chip ESD protection to enable high-speed Ethernet speed in cars
How Synopsys and Infineon Are Advancing Vehicle Virtualization and AI-Fueled Features
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