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Powering RISC-V SoC With 1 To 1000s Cores
Charlie Su, CTO & EVP, Andes Technology
2019 RISC-V CON Silicon Valley
Posted on Thursday Nov. 07, 2019
Andes Technology Corp. Channel
Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
45:53
The Next Generation RISC-V Processors AndesCore™ 27, 45 Series
26:45
Status Update of RISC-V P Extension Task Group
7:30
Fast yet Low Power RISC-V Core IP for SoC Designers
20:20
Andes Technology at IP SoC Santa Clara 2019
3:16
Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips 45:53
The Next Generation RISC-V Processors AndesCore™ 27, 45 Series26:45
Status Update of RISC-V P Extension Task Group7:30
Fast yet Low Power RISC-V Core IP for SoC Designers20:20
Andes Technology at IP SoC Santa Clara 20193:16