SoC teams 8-bit core with FPGA

• Ethernet and TCP/IP networking protocols require manipulating large data pointers and 32-bit addresses;

• libraries for link control functions tend to be large and complex, and are written in higher-level languages, often requiring the additional overhead of an operating system; and

• buffering high-speed data streams necessitates the use of direct-memory-access (DMA) channels like those typically only offered by 16- or 32-bit processors.

Despite those factors, our engineering team took a different approach in designing the core of Cirronet's WaveBolt, a wireless broadband Internet access system. By exploitin g the system-level integration, large memory and flexible interface capabilities of an Atmel FPSLIC programmable system-on-chip, we were able to distribute the workload efficiently between the processor and the FPGA, achieving exceptional throughput with an 8-bit processor. Atmel's FPSLIC includes an 8-bit AVR processor, 40k gates of FPGA, 36 kbytes of dual-port SRAM and a variety of on-board peripherals.

We probably wouldn't have considered an 8-bit processor if not for our previous success designing a simplified 8-bit wireless protocol for industrial applications that was based on Atmel's AVR microprocessors. We found that our existing industrial-radio technology met many of the demands for last-mile Internet: long range, low cost and robustness to interference. By leveraging an existing bug-free code base, we were able to cut months off our schedule.

Like its industrial predecessors, the WaveBolt system employs a star-shaped radio network topology. At the center of the star is a ba se unit, typically located atop a tower or tall building, which leads and coordinates transmissions with up to 62 remote units mounted at subscribers' homes or businesses. As many as 16 of these basestations can be co-located at a single access point to support up to 960 remote subscribers (customer-premises equipment). The WaveBolt system is based on spread-spectrum frequency-hopping technology, so radios co-located near each other do not interfere destructively as they would for wideband, fixed-frequency signals.

Unlike peer-to-peer networks, in which the data headers must include both the source and destination address and keep track of multiple levels of routing information, in a star network all traffic to and from the remote CPEs comes from or goes to a single location. This allowed us to use a very lightweight and efficient time-division multiple-access (TDMA) link control protocol with 8-bit address and simple automatic repeat-request error management. Short headers mean we spend most of our time actually sending data, resulting in high throughput. WaveBolt has a raw transfer speed of 1.23 Mbits/second, with typical user-experienced download and upload speeds of 700 and 250 kbits/s.

The workload is distributed between the FPSLIC's on-chip AVR microprocessor and the FPGA in the following way: The AVR microprocessor in the FPSLIC device performs all the processing for hop coordination, link control, authentication, frame sequencing and packet assembly. Data frame chores like parsing control packets and computing TDMA slot periods and checksums demand a lot of processor muscle.

The FPSLIC's AVR is unusually capable in this regard for an 8-bit machine. It has a RISC architecture, single-cycle instruction times and features usually found only on much bigger processors, including a generous set of 32 orthogonal registers that simplify task switching, 10 addressing modes and a very useful set of 16-bit pointer registers. Since it executes directly from fast on-board SRAM, it can run at up to 20 Mips. It was the only 8-bit processor we evaluated with enough performance for the application.

Our digital radio has two high-speed, real-time serial interfaces to manage. We needed some way of offloading to hardware the heavy chores of loading and unloading each of these bytes individually from the peripherals and moving them from one buffer to another. An 8-bitter trying to do this alone would be overtasked.

However, by offloading the tasks to the on-chip FPGA, we were able to achieve the requisite throughput. Both the FPGA and the AVR processor on the FPSLIC device interface directly to 36 kbytes of on-chip, dual-port, program/data SRAM, allowing both the processor and the FPGA to read and write to the memory independently and simultaneously. That capability allowed us to build a custom DMA engine in the FPGA that automatically handles all the data buffering without intervention from the processor.

Other MAC functions were implemented in the FPG A and tied directly to the memory interface where possible. They included standard signal-processing functions such as timing recovery, receive-byte framing, a transmit sequencer and a high-speed custom serial port.

Critical integration

The system-level integration of the FPSLIC device was critical to the implementation. For example, our DMA system controller would have been much more complex to design, would have been slower and would have required more logic if we had been forced to use an external FPGA and memory. The large SRAM size (36 kbytes) was also a a key factor. Internet packets are typically 1 to 2 kbytes, and we needed enough memory to store a reasonable number of them in order to keep multiple connections afloat while weathering the occasional need for retransmissions. Another benefit, from an integrated approach, is that power consumption and heat dissipation are much lower.

We think the WaveBolt design proves that there is more than one approach to implementing broadband wireless. Because we could fit our entire digital baseband controller on one chip instead of a multichip 32-bit solution, we were able to reduce our materials costs. Coupled with our strategy of installation by the subscriber, or "no truck rolls," Internet service providers are able to deploy last-mile wireless Internet service with this product for as low as $400 per subscriber, instead of more than $1,000 per subscriber using systems based on more traditional methodologies.

Although there may be broadband applications that call for a more powerful network platform, plenty of applications could benefit from our streamlined approach. It is a single-chip, off-the-shelf solution, rather than a three- or four-chip solution (processor, memory, ASIC or FPGA). The cost is about one-third that of a 32-bit solution. And 8-bit designs are quicker to implement and debug, providing a competitive advantage in getting product to market.

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