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MSIM Simulator with 5X~10X Speedup for Characterizing CCS Timing Model of Cell Library (Wednesday May. 21, 2008)
Legend Design Technology, Inc. today announced that its MSIM, a high-accuracy Spice circuit simulator, has been upgraded for efficient characterization of CCS (Composite Current Source) model used in cell library characterization in SoC designs.
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Synopsys Donates Proven VMM Methodology Library and Applications to Accellera (Monday May. 12, 2008)
Synopsys today announced that it is donating its complete implementation of the proven VMM verification methodology for SystemVerilog, including the VMM Standard Library and VMM Applications, to Accellera to enable verification interoperability standardization.
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NextIO Standardizes on VMM Methodology and Synopsys VCS for Next-Generation I/O Virtualization Chip (Thursday May. 08, 2008)
Pairing the VMM methodology with the VCS tool enabled NextIO to efficiently build highly accurate system-level and unit-level simulation environments that quickly identify design bugs. This complete verification environment enabled NextIO to achieve first-pass functional silicon success.
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Cadence Delivers Silicon-Ready Reference Methodologies for ARM Cortex-A9 Processor (Friday May. 02, 2008)
Cadence Design Systems, Inc. today announced the immediate availability of multiple, silicon-ready RTL to GDSII implementation flows based on the Cadence® Encounter® digital IC design platform, for the ARM® Cortex™-A9 processor.
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Synplicity Launches ReadyIP Program: The Industry's First Universal, Secure IP Flow for FPGA Implementation (Tuesday Apr. 15, 2008)
The ReadyIP program delivers the industry’s first and complete universal, encrypted design methodology for FPGA implementation, allowing users to incorporate and easily integrate IP from several third-party vendors within their designs using the Synplify Pro® and/or Synplify® Premier solutions, Synplicity’s industry-standard synthesis environments.
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Synplicity Introduces System Designer: System-Level Implementation and IP Integration Tool for FPGA Design (Tuesday Apr. 15, 2008)
The System Designer™ capability allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then easily implement it into a variety of FPGA vendor devices, including those from Actel, Altera, Lattice Semiconductor and Xilinx.
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ClioSoft Introduces Enterprise Edition of the SOS Design Data Collaboration Platform (Friday Apr. 11, 2008)
SOS Enterprise Edition is aimed at addressing the needs of large distributed enterprises by providing integrated design data management for a variety of EDA tools, easing management of hierarchically distributed designs, facilitating reuse of intellectual property and ensuring immediate, live, virtual onsite support when needed.
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NXP Semiconductors and IPextreme Launch Ground-breaking Methodology for Semiconductor IP Design (Wednesday Apr. 02, 2008)
IPextreme and NXP Semiconductors today announced the availability of NXP’s internally-developed CoReUse methodology and QCore™ tool for licensing to the entire semiconductor industry through IPextreme.
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Synopsys Extends Design Compiler Topographical Technology to Predict and Alleviate Routing Congestion (Monday Mar. 31, 2008)
Design Compiler Graphical is the industry's first synthesis solution that predicts circuit congestion "hot spots" early in the design flow, provides designers with visualization of the congested circuit regions and performs synthesis optimizations to minimize congestion in these areas.
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Mentor Graphics Expands Questa Functional Verification Platform with Questa Codelink for Processor-Driven Tests (Thursday Mar. 27, 2008)
The Questa Codelink product is an integrated, source-level debug environment targeting processor driven tests.
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Numetrics Unveils NMX-ERP 3.0, Next Generation ERP Software for Semiconductor IC Development Organizations (Monday Mar. 24, 2008)
New Software Measures Schedule Risk of 45nm IC Projects, Delivers Enhanced Staffing & Schedule Estimates, Introduces XML Interface for Enterprise-wide Integration
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The MathWorks Expands Product Portfolio for Electronic System Verification (Monday Mar. 24, 2008)
EDA Simulator Link Products Now Provide System-Level Verification Workflow for Hardware Simulators from Synopsys, Mentor Graphics, and Cadence Design Systems
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Mentor Graphics New Version of Platform Express Supports IP-XACT 1.4 Specification from The SPIRIT Consortium (Tuesday Mar. 18, 2008)
Mentor Graphics today announced the immediate availability of a new version of Platform Express™ with full support for the IP-XACT 1.4 IP databook specification, new mixed-level RTL and ESL design capabilities, and a new portable generator format.
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Synopsys IC Compiler Routing Qualifies for TSMC's 45-Nanometer Process (Monday Mar. 17, 2008)
The qualification by TSMC offers designers an assured path to design- rule-correct physical implementation. Multiple 45-nm designs utilizing IC Compiler with TSMC technology are already underway.
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New IP-XACT Specification to Aid Design and Advanced Verification (Monday Mar. 10, 2008)
IP-XACT Addresses Electronic System-Level Design and Portable Generators with Automated Design Processes
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Synopsys Announces Multi-Core Initiative to Accelerate Design Time-To-Results (Monday Mar. 10, 2008)
Synopsys today announced its multi-core initiative to deploy advanced parallel, threaded and other optimized compute technologies across its Discovery™ Verification and Galaxy™ Design platforms, and Design for Manufacturing (DFM) solutions.
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eASIC Integrates Front-End from Interra to Accelerate Deployment of Nextreme Structured ASICs (Tuesday Mar. 04, 2008)
Interra Systems announced successful integration of Concorde, a Verilog, VHDL and mixed language parser, elaborator and synthesis front-end into the eX and eWizard design tools for the Nextreme 90nm family of structured ASICs from eASIC.
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OCP-IP Unveils CoreCreator II (Tuesday Mar. 04, 2008)
CoreCreator II features verification IP and command-line based tools for validating Open Core Protocol (OCP) implementations, reducing design time and risk, and enabling rapid time to market.
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Magma Introduces Titan -- First Platform to Combine Full-Chip, Mixed-Signal, Analysis and Verification for IC Design (Thursday Feb. 28, 2008)
Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in efficiency and productivity for analog designers.
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Synopsys Introduces the Eclypse Low Power Solution (Monday Feb. 25, 2008)
Synopsys today announced the Synopsys Eclypse™ Low Power Solution, the industry's most comprehensive suite of proven system-level, verification, implementation and signoff tools, intellectual property (IP), methodologies and services for low power chip development.
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OneSpin Solutions Dramatically Boosts Formal Verification Productivity With New GapFreeVerification Process (Monday Feb. 18, 2008)
The new process delivers predictable, repeatable verification results for complex modules and IP, accelerating the gap-free formal verification that ensures first-time error-free operation.
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Mentor Graphics Delivers Breakthrough in Verification Intelligence (Monday Feb. 18, 2008)
Mentor Graphics today announced the Questa® Multi-view Verification Components product and the inFact™ intelligent testbench automation tool – two new solutions that use breakthrough technologies to speed up verification and drastically improve verification coverage of today’s SoC (System on Chip) designs.
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Cadence and Mentor Enhance Open Verification Methodology and Expand Community Activities to Support Rapidly Growing User Base (Thursday Feb. 14, 2008)
Distributed under the standard open-source Apache™ 2.0 license, the OVM source code, usage examples, and documentation may be downloaded free of charge from OVM World.
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Dolphin Integration clears the conundrum of Class D versus Class AB (Monday Feb. 04, 2008)
The pressure to lowering the power consumption leads system designers to investigate different architectures for audio amplifiers. They naturally investigate class-D amplifiers as the new El-Dorado for low power operation. Indeed Class-D technology is usually appraised for its high efficiency.
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Magma, Mentor Graphics and Synopsys Deliver Unified Power Format-Based Products (Monday Jan. 21, 2008)
The UPF standard enables end users to create a consistent, succinct, unified description of the low power design intent for use by EDA tools offering advanced features for design and verification of today's low power integrated circuits (ICs)
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Cadence and Mentor Announce Immediate Availability of the Open Verification Methodology (Wednesday Jan. 09, 2008)
The OVM, based on IEEE Std. 1800(TM)-2005 SystemVerilog standard, is the first open, language interoperable, SystemVerilog verification methodology in the industry. The OVM provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces.
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Averant and AerieLogic to Ease the Usage of Formal Property Verification (Monday Dec. 17, 2007)
Averant and AerieLogic jointly announced the immediate availability of AerieLogic's Formal Verification IPs integrated with Averant's high capacity formal property checker Solidify
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OneSpin Solutions Delivers First Equivalence Checker Dedicated to FPGA Synthesis Verification (Monday Dec. 10, 2007)
OneSpin Solutions today announced its stand-alone 360 EC-FPGA equivalence checker – the industry's first sequential equivalence checking solution dedicated to and priced for the FPGA market
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Cadence and ARM Deliver Reference Methodologies for Multicore and Low-Power Devices (Wednesday Dec. 05, 2007)
Cadence Design Systems, Inc. and ARM today announced the availability of two new implementation reference methodologies jointly developed by the companies, one for the ARM11™ MPCore™ multicore processor and the other for low-power implementation of the ARM1176JZF-S™ processor, which incorporates ARM® Intelligent Energy Manager (IEM™) technology
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Cadence Boosts Engineers' Productivity with Advances in Enterprise Verification Offering (Monday Dec. 03, 2007)
New Aspect-Oriented Generation Engine and Advanced Transaction-Based Acceleration; Supports Open Verification Methodology for SystemVerilog