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Arithmatica Releases Major Updates to Datapath Synthesis Tools and Intellectual Property (Tuesday Nov. 20, 2007)
Arithmatica, the datapath design company, today announced the release of major updates to its flagship products CellMath Designer and CellMath IP.
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Temento Launches an Innovative Business Model for Its 'Dialite' Debug Platform (Monday Nov. 12, 2007)
Temento Systems ® SA announced today a Debug-on-Demand model available on its website in order to decrease the cost of debug tools for FPGA designs, while having access to advanced features.
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e2v adopts EdXact's Jivaro tools (Tuesday Nov. 06, 2007)
e2v is using Jivaro to help verifying its next generation high speed A/D converters, which is developed using Jazz Semiconductor’s advanced SiGe BiCMOS 0.18-micron process.
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CoWare Introduces First ESL 2.0 Technology Release for the Design of Processor- and Software-Intensive Electronic Platforms (Monday Nov. 05, 2007)
New Release Greatly Simplifies the Adoption of ESL Technologies and Improves Design Efficiency Required to Deploy ESL and Accelerate Design Innovation
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DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry's First High-level DFT Sign-off Methodology (Monday Oct. 22, 2007)
HiDFT-Scan addresses a major problem in nanometer electronic circuit design: The ability to fulfill DFT closure requirements at the gate level has come to a standstill. As feature sizes have shrunk, designs have become more complex and the volume of test patterns has increased to the point where it is unrealistic to perform verification tasks at the gate level.
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Genesys Testware Adds Automated Batch-Mode Diagnosis and Characterization of Embedded Memories (Wednesday Oct. 17, 2007)
Unlike competing solutions, ArraytestMaker Diagnostics works with any Automatic Test Equipment (ATE) without any hardware or software modification. Batch-mode operation simplifies test data management with globally distributed manufacturing test facilities. In contrast to other solutions, ArraytestMaker Diagnostics does not require any change in existing design flows because it works with any Test Access Port (TAP) controller.
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Magma Unveils Talus ATPG and Talus ATPG-X – Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression (Monday Oct. 15, 2007)
Advanced ATPG products support simultaneous analysis of multiple fault models, leverage multi-threading and on-chip compression to improve quality and reduce turnaround time and costs of nanometer ICs
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Mentor Graphics and Altera announce Catapult C Synthesis Accelerated Libraries for High-Performance DSP Hardware in FPGA (Thursday Oct. 11, 2007)
The design flow, based on Altera’s Accelerated Libraries for Mentor Graphics’ Catapult® C Synthesis tool, delivers 50-80 percent DSP Fmax performance improvements, provides a low-effort path to dedicated DSP hardware creation, and gives companies a cost-per-channel advantage over expensive, power-hungry discrete digital signal processors for high-performance applications.
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Jasper Design Automation Announces JasperGold(R) Verification System v4.5 Featuring Liveness Property Support, Improved Modeling and Faster Engine Performance (Wednesday Oct. 03, 2007)
In release 4.5, JasperGold delivers high-leverage, low-effort formal verification by deploying Jasper's unique Proof Accelerators(TM), Lossless Abstractions(TM), and patented Formal Scoreboard(TM), which provide more robust performance, increased ease-of-use and unmatched end-to-end proof capacity.
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Carbon Design Systems Unveils Carbon Model Studio (Monday Oct. 01, 2007)
Complete Solution for Automatic Generation, Validation, Implementation of Pre-Silicon Hardware-Accurate Software Models
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Synopsys HSPICE Simulator Accelerates ARM's 45-Nanometer Physical IP Development (Wednesday Sep. 26, 2007)
Synopsys today announced that significant performance improvements in the latest version of its HSPICE® simulator enabled ARM to accelerate delivery of highly optimized memory and standard cell building blocks for systems-on-chip (SOCs).
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NEC Electronics America Uses Cadence Encounter for High-performance, Low-power ARM11 Processor (Tuesday Sep. 25, 2007)
Cadence Encounter Synthesis and Implementation Technologies Now One of NEC Electronics America's Tapeout Methodologies of Choice for ARM Processor Implementations
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Mentor Graphics Announces Precision RTL Plus for FPGA Synthesis -- Vendor-Independent Solution for Breakthrough Productivity (Monday Sep. 24, 2007)
The new tool provides several industry-first capabilities that enable every designer, regardless of level of expertise, to reach timing closure faster, minimize the impact of late cycle design changes, and make efficient use of FPGA architectural blocks
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Magma and UMC Deliver Robust Physical Verification and DFM Solution for 65 nm (Thursday Sep. 20, 2007)
The two companies completed joint qualification of Magma's QuartzTM DRC, Quartz LVS and Quartz DFM for UMC's advanced processes and development of foundry-validated runsets and models that support the flow, which is tuned to detect design problems so they are corrected quickly.
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ARC and Cadence Offer New Low-Power Design Methodology for Demanding Mobile Applications (Monday Sep. 10, 2007)
This low-power reference design methodology (LP-RDM) together with the Cadence® Low Power Solution ensures that ARC’s new Energy PRO technology is captured in RTL and implemented consistently throughout the design flow to GDSII. Users of the reference design flow may achieve up to a four-fold reduction of IP core power.
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LogicVision Provides Desktop Silicon Characterization and Diagnostics Solution with the Introduction of Silicon Insight (Monday Sep. 10, 2007)
Silicon Insight, running on a Linux PC or laptop, interfaces to a customer’s device or performance board through simple USB-to-JTAG cable interface hardware to provide an interactive graphical environment for characterization, debug and diagnosis of silicon devices incorporating LogicVision’s embedded test IP.
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Dolphin Integration announces the availability in September 2007 of Third Generation Schematic Link EDitor, named SLED (Monday Sep. 10, 2007)
Compared to current solutions, SLED is both framework independent and open to bridging with EDA tools: it maximizes interoperability at different levels of the design chains.
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Averant Announces Release of SolidPC 2.0, ARM AMBA 3 Assured Status (Wednesday Aug. 29, 2007)
SolidPC's combination of ARM technology-developed and endorsed AMBA rule sets, the Solidify First in Formal(tm) property checking engine, and a purpose built, easy to use, graphical user interface makes SolidPC the tool of choice for AMBA protocol verification.
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LogicVision Announces New Release of Its Embedded SerDes Test Solution (Wednesday Aug. 29, 2007)
LogicVision today announced major enhancements to its industry-leading embedded SerDes test solution to help customers cope with the cost and challenges of testing multi-channel, high-speed, serial I/Os. The new release provides more accurate measurements and the ability to perform bit error rate testing (BERT).
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New Kit From Cadence Cuts Risk and Time for Adopting Functional Verification Methodology (Monday Aug. 27, 2007)
The kit provides complete example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts and libraries -- all proven on a wireless segment representative design and delivered through applicability consulting.
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Mentor Graphics Offers Sonics(R) SMART Interconnect(TM) Solutions (Wednesday Aug. 22, 2007)
Sonics announced today that Sonics SMART Interconnect solutions are now available as library elements for Mentor Graphics' Vista(TM) and Visual Elite(TM) products. Mentor Graphics now offers a complete configuration, analysis and verification of SystemC SoC platforms based on Sonics SMART Interconnect solutions.
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LogicVision Announces Production Release of Memory Built-In Self-Repair and ScanBurst At-Speed Scan Solution Integrated With Mentor Graphic's FastScan and TestKompress (Tuesday Aug. 21, 2007)
The new release provides comprehensive RTL insertion support for all BIST capabilities, including full support for the Verilog 2001 language, production releases of the company's memory built-in self-repair solution, ETMemory(TM)-Repair, and the company's ScanBurst(TM) at- speed scan solution.
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Cadence Extends DFM Solution with Acquisition of Design-side Litho and Variability Leader Clear Shape Technologies (Friday Aug. 17, 2007)
Combined with Cadence's existing DFM methodologies and capabilities, the acquisition uniquely positions Cadence® as the only EDA company that can deliver manufacturing awareness and lithographic correctness for all layers in an IC from transistor through interconnect, in designs ranging from SoCs to full-custom and all design domains including analog, digital and mixed signal.
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Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology (Thursday Aug. 16, 2007)
The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. It delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will include a robust class library and be available in source code format.
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Certess Certitude Improves Verification Strategy at Juniper Networks (Thursday Aug. 02, 2007)
Certess, Inc. today announced that Juniper Networks, the leader in high-performance networking, has adopted Certitude, the first commercial functional qualification software product for companies developing systems on a chip (SoCs) or integrating intellectual property (IP) blocks.
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Beach Solutions Auto-generates Firmware for Concurrent SoC Engineering (Wednesday Aug. 01, 2007)
Beach Solutions, the leading provider of commercial tools to manage addressable registers and auto-generate SoC (System-on-Chip) design integration deliverables, introduces their enhanced EASI Code product.
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ECS develops new technology to facilitate System-on-Chip (Monday Jul. 30, 2007)
Professor Bashir Al-Hashimi and his team at the University’s School of Electronics & Computer Science (ECS) have developed NIRGAM (Network-on-Chip Interconnect RoutinG and Applications Modelling), a simulator which will make it possible to easily connect up the various cores which exist within a System-on-Chip (SoC).
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Knowlent Brings Advanced Analog/Mixed-Signal Verification Environment to Users of Synopsys Discovery AMS solutions (Monday Jul. 23, 2007)
Knowlent Corporation today announced the release of the Opal TBE(TM) test bench development and simulation control environment that supports all circuit simulation technologies from Synopsys, Inc. Opal TBE will provide Synopsys users with a graphical user interface for analysis, characterization and verification of complex analog/custom blocks used in system-on-chip (SOC) designs implemented in the latest nanometer silicon technologies.
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Faraday Technology Enhances PowerSmart Design Flow to Include Sequence's RTL Power Analysis Tool (Wednesday Jul. 18, 2007)
Faraday Technology announced today that it has further enhanced the PowerSmart ultra-low power ASIC design flow to include a front-end tool, which allows designers to perform power trade-off and optimization at the RTL level. Sequence Design, a leader in providing advanced power-aware design tools, will be the supply partner of this tool.
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Inovys Introduces YieldVision(TM), a Revolutionary Suite of Analysis Tools for Advanced SOCs (Tuesday Jul. 10, 2007)
YieldVision provides customers with the ability to efficiently triage, or reduce, large quantities of electrical failures into specific logical faults, which results in fast localization of the root cause physical defects.