Voltage Monitor with Digital Output (Multi-domain supply monitoring), TSMC N3E
1606 Results (121 - 160) |
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Next generation intelligent wearables enabled by sureCore's ultra-low power memory
Oct. 05, 2021 - As the market for wearable electronics and earbuds grows dramatically, architects are adding more features or ‘smarts’ to create product differentiation. The additional intelligence means that designers are required to add more embedded memory to the chip resulting in increased power demands. -
GF and Synopsys Deliver New Reference Flows for GF 22FDX Process: Cloud-Qualified and First Automotive Flow for ASIL-D Designs
Sep. 16, 2021 - GlobalFoundries® (GF), the global leader in specialty semiconductor manufacturing, and Synopsys, Inc. (Nasdaq: SNPS) today announced that GF has qualified two key Synopsys reference flows for its 22FDX™ process -
QuickLogic Announces New eFPGA Contract
Sep. 02, 2021 - QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, today announced that it has won a $2 million eFPGA Contract. -
sureCore announces development of cryo-CMOS IP that will unlock Quantum Computing's potential
Sep. 01, 2021 - sureCore, the ultra-low power embedded IP specialist, has announced that it is developing a range of CMOS IP suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications. -
Engineering recruitment stepped up by surge in demand for ultra-low power memory solutions
Aug. 24, 2021 - sureCore, the ultra-low power memory specialists, is surfing the wave of demand for ever more intelligent wearable devices that are only possible if they use the company’s specially designed SRAM IP that can cut memory power requirements by up to 50%. -
Motivo, Inc. Raises $12 Million Series A to Accelerate AI-Enabled Chip Design and Improve Manufacturing Yields
Aug. 16, 2021 - Motivo today announced it raised a $12 million Series A financing round led by Intel® Capital, along with other new investors Storm Ventures and Seraph Group as well as participation from Inventus Capital and other existing investors that include multiple IC industry C-suite executives. -
AccelerComm joins DARPA Toolbox initiative for advanced communications research projects
Aug. 05, 2021 - AccelerComm, the company supercharging 5G with physical layer IP which increases spectral efficiency and reduces latency, today announced an agreement with the U.S. Defense Advanced Research Projects Agency (DARPA). -
Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites
Jul. 19, 2021 - Imperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites. -
Synopsys Strategic Partnership with Samsung Foundry Accelerates Access to Transformative 3nm GAA Technology
Jun. 28, 2021 - ynopsys, Inc. (Nasdaq: SNPS) today announced that the Synopsys Fusion Design Platform™ has enabled Samsung Foundry to achieve first-pass silicon success for an advanced, high-performance and multi-subsystem system-on-chip (SoC), validating the extended power, performance and area (PPA) benefits of ... -
CEA-Leti Collaborates with Siemens to Launch Process Design Kit that Supports Multiple Technologies, Simplifies Creation of Optical Circuits
Jun. 17, 2021 - CEA-Leti, a research institute at CEA, today announced that it has collaborated with Siemens Digital Industries Software to offer an updated process design kit (PDK) that enables photonic designers to select multiple methodologies, including layout centric, schematic driven and layout automation and ... -
sureCore & Intrinsic Announce Collaboration to Bring Novel RRAM Technology to Market
Jun. 11, 2021 - Intrinsic and sureCore are collaborating to deliver commercial memory solutions using sureCore’s patented memory architectures and Intrinsic’s novel RRAM cell. -
SmartDV Announces Support for ARINC Standards with Design and Verification IP
Jun. 03, 2021 - SmartDV™ Technologies, the leader in Design and Verification Intellectual Property (IP), today announced support of the ARINC standards with its Design and Verification IP. -
Cadence Collaborates with TSMC to Accelerate Mobile, AI and Hyperscale Computing Application Development on N3 and N4 Processes
May. 31, 2021 - Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it is expanding its collaboration with TSMC to accelerate mobile, AI and hyperscale computing application design using the integrated Cadence® digital flow and custom/analog tool suite on TSMC’s N3 and N4 process technologies. -
Synopsys Digital and Custom Design Platforms Certified for TSMC's Latest 3nm Process Technology
May. 26, 2021 - Synopsys today announced that TSMC has certified Synopsys' digital and custom design solutions based on TSMC's latest design-rule manual (DRM) and process design kits for its advanced 3-nanometer (nm) process technology. -
Synopsys Enables First-Pass Silicon Success for Early Adopters of Next-Generation Armv9 Architecture-based SoCs
May. 25, 2021 - Synopsys today announced multiple SoC tape-outs at early adopters of the next-generation Arm® Cortex®-X2, Cortex-A710, and Cortex-A510 CPUs based on Armv9, Arm Mali™-G710 GPUs and Arm DynamIQ Shared Unit-110 were achieved using Synopsys' portfolio of industry-leading solutions. -
Thalia's AMALIA Technology Analyzer de-risks Analog IP reuse for major IP houses and IC manufacturers
May. 18, 2021 - Thalia Design Automation, an IP reuse company and experts in the development and deployment of automation solutions for Analog & Mixed Signal IP Reuse, today announced further upgrades and enhancements to its Technology Analyzer. -
Synopsys and Arm Deliver Comprehensive Solutions to Increase Performance and Accelerate Time-to-Market for High-Performance Computing, Data Center and AI SoCs
Apr. 27, 2021 - Synopsys, Inc. (Nasdaq: SNPS) today announced that Arm and Synopsys have expanded their strategic collaboration to deliver optimized design, verification, silicon IP, software security, quality solutions and reference flows for Arm®-based system-on chips (SoCs), including the Arm Neoverse™ V1 and ... -
Defacto Technologies Announces SoC Compiler, v9
Apr. 26, 2021 - Defacto Technologies today announces v9 of their EDA software offering, SoC Compiler, replacing the STAR product name. -
sureCore Unveils New Low Voltage Register Files
Apr. 22, 2021 - SureCore Limited today unveiled a configurable register file compiler that offers industry-leading 60% dynamic power savings over current off-the-shelf solutions. -
Movellus Launches Maestro Intelligent Clock Network Platform for SoC Designs
Apr. 20, 2021 - Movellus, Inc. today announced its Maestro™ Intelligent Clock Network platform that intelligently orchestrates clock distribution in SoC designs. The platform provides critical clocking capabilities that address complex clock distribution requirements in modern SoCs, including AI applications in the ... -
Arteris IP Welcomes Back Veteran Laurent Moll as Chief Operating Officer
Apr. 14, 2021 - Arteris IP today announced it is proud to welcome Laurent Moll as Chief Operating Officer (COO). Laurent will be responsible for managing all aspects of engineering functions and operations at Arteris IP. -
Cadence Collaborates with Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm
Apr. 09, 2021 - Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has optimized the Cadence® digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm. -
Arm's solution to the future needs of AI, security and specialized computing is v9
Mar. 31, 2021 - Armv9 is the first new Arm architecture in a decade, building on the success of Armv8 which today drives the best performance-per-watt everywhere computing happens. -
Imperas releases free ISS for RISC-V CORE-V developers in the OpenHW ecosystem
Mar. 29, 2021 - Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today made available the first release of riscvOVPsimCOREV as free ISS (Instruction Set Simulator) based on the Imperas reference models of the OpenHW Groups processor RISC-V core IP. -
Siemens delivers next-generation, comprehensive hardware-assisted verification system
Mar. 26, 2021 - Siemens Digital Industries Software today unveiled its next-generation Veloce™ hardware-assisted verification system for the rapid verification of highly sophisticated, next-generation integrated circuit (IC) designs. -
Valtrix and Codasip Cooperate on Verification of RISC-V Systems
Mar. 23, 2021 - Valtrix Systems, the provider of design verification products for building functionally correct CPU and system-on-chip implementations, and Codasip, the leading supplier of customizable RISC-V® embedded processor IP, announced today that they are cooperating on the verification of RISC-V-based systems. ... -
Tortuga Logic Announces Expansion of Product Portfolio with Development of New Security Governance Platform
Mar. 11, 2021 - Tortuga Logic® Inc, a cybersecurity company that has pioneered semiconductor chip security solutions, today announced the development of a Security Governance Platform (SGP), expanding its portfolio of advanced hardware security solutions. -
Thalia successfully completes 20th 22nm analog IP reuse engagement
Mar. 04, 2021 - Thalia Design Automation, a leading IP reuse company and experts in targeted automation for analog and mixed signal design and migration, today announced the successful completion of its 20th analog IP portfolio migration into the 22nm technology node. -
Synapse Design and Flex Logix Tape Out Mutual Customer ASIC on a New Process in Less Than a Year Using Embedded FPGA (eFPGA) Technology
Feb. 01, 2021 - Flex Logix Technologies and Synapse Design Automation today announced that they have successfully taped out a new ASIC for a mutual customer using the EFLX eFPGA IP ported to a new process in less than a year. -
Imperas Leads The RISC-V Processor Verification Ecosystem
Jan. 25, 2021 - Imperas Software today announced the latest addition to the Imperas RISC-V Verification IP (VIP) solutions with the Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D). ... -
Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements
Jan. 20, 2021 - Aldec has enhanced Active-HDL™ to support new features within VHDL-2019 (IEEE 1076-2019). These features simplify the language, lift certain restrictions that were present in earlier versions and introduce new application programming interfaces (APIs). -
Andes Technology and Rafael Microelectronics Announce a Strategic Partnership to Provide High Power Efficiency Wireless IP Solutions for IoT Devices
Jan. 14, 2021 - Andes Technology, a global leader in 32/64-bit RISC-V CPU core solutions, and Rafael Microelectronics, a leading provider for RF IP and wireless communication subsystem cores, are announcing a strategic partnership to bring a wireless IoT connectivity solution based on RISC-V cores to the industry. -
MosChip Technologies Achieves ISO 9001:2015 Certification
Dec. 21, 2020 - MosChip Technologies Limited, a semiconductor and system design services company, announced today that it has achieved ISO 9001:2015 certification. -
Imperas releases new RISC-V Processor Verification IP to drive RISC-V adoption forward with a flexible methodology for all SoC adopters
Dec. 10, 2020 - Imperas Software Ltd., the leader in RISC-V processor verification solutions, today announced significant enhancements to its RISC-V processor hardware design verification solutions -
C-DAC Selects Valtrix STING For Design Verification Of RISC-V Based Microprocessors
Dec. 08, 2020 - Valtrix Systems announced today that Centre for Development of Advanced Computing (C-DAC), a premier R&D organization of Government of India, has licensed STING for the verification of RISC-V based designs being developed for use in a number of strategic sectors. -
Dolphin Design unveil a new and improved version of its Power Controller IP - MAESTRO - to speed-up energy-efficient SoC design
Dec. 07, 2020 - With the growing chip complexity observed in many market segments, in addition to a need for longer battery life, SoC design teams are forced to adopt advanced power management techniques to improve the energy-efficiency of their devices. -
Cadence Wins Four 2020 TSMC OIP Partner of the Year Awards
Nov. 02, 2020 - Cadence achieves recognition for joint development of N3 design infrastructure, 3D-IC design productivity solution, timing signoff in the cloud design solution and DSP IP -
Movellus Joins GLOBALFOUNDRIES Ecosystem Program, as Partner Providing Application-Optimized PLLs, DLLs, & Comprehensive Clocking Solutions
Nov. 03, 2020 - Movellus’ fully synthesizable and quickly customizable PLLs/DLLs are available to GF customers around the world with the goal of further enabling their designs and ultimately reducing their time-to-market. -
Synopsys and Samsung Release Certified 3nm Gate-All-Around AMS Design Reference Flow for Early Design Starts
Oct. 28, 2020 - Synopsys, Inc. (Nasdaq: SNPS) today announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform. -
Synopsys 3DIC Compiler Enables Samsung Tapeout of Advanced Multi-die Packaging of High-Bandwidth Memories for HPC Applications
Oct. 22, 2020 - Synopsys, Inc. (Nasdaq: SNPS) today announced that its 3DIC Compiler solution enabled Samsung Foundry to design, implement and tape out a complex 5-nanometer SoC featuring eight high-bandwidth memories (HBMs) in a single package.