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IP / SOC Products News

• Denali Software and Tokyo Electron Device Unveil New DFI Compatible DDR2 SDRAM PHY for Xilinx FPGA (Thursday Sep. 20, 2007)
  Tokyo Electron Device, Ltd. (TED) ASIC customers now have access to DDR PHY designs, in 90-nm process technologies and below, that integrate seamlessly with other DFI compatible designs, including Denali's Databahn(TM) DDR memory controller products.
  
  
• Fujitsu and Denali Software Collaborate to Develop DFI Compatible DDR PHY Macro (Wednesday Sep. 19, 2007)
  The DDR PHY utilizes the DFI specification which defines a common interface between the conventional proprietary memory controller logic and DDR PHY designs, which reduces design and integration costs for developing DDR DRAM memory systems, and reduces overall time-to-market.
  
  
• IMEC Sets New Record for 9bit, 50MSamples/s SAR ADC with a Figure of Merit of 65fJ (Wednesday Sep. 19, 2007)
  The novel IMEC SAR ADC design is especially suited for nomadic applications in the IT realm. It is implemented in pure digital CMOS technology, making it very well suited for scaling to the 45nm CMOS node and below. The design is available as 'white box IP' for transfer to the industry.
  
  
• Chipidea Delivers First TSMC Qualified USB High-Speed PHY IP on 65nm GP Process Technology (Tuesday Sep. 18, 2007)
  The certified High-Speed USB PHY core runs at 2.5 volts and is compliant with the USB 2.0 standard, including 5 volt protection on the D+ D- ports. The unique analog programmability of the IP is a key feature that enables system-on-chip (SoC) designers to fine tune the complete system for optimized performance.
  
  
• Xilinx Enhances Wireless Infrastructure Solutions With New Virtex-5 FPGA IP for CPRI and OBSAI Standards (Monday Sep. 17, 2007)
  Xilinx today announced immediate availability of two high performance wireless connectivity LogiCORE solutions optimized for Xilinx(R) 65nm Virtex(TM)-5 LXT and SXT FPGAs, compliant with CPRI v2.1 and OBSAI RP3 & RP3-01 v4.0 connectivity standards.
  
  
• Actel Offers Free, Optimized ARM Cortex-M1 Processor for Industry's Lowest Power FPGA Family (Monday Sep. 17, 2007)
  Enabling system designers to dramatically extend the battery life of their handheld and portable designs, Actel Corporation today announced it has optimized the ARM® Cortex™-M1 processor core for its IGLOO family of field-programmable gate arrays (FPGAs).
  
  
• Impinj preps 65-nm NVM for October launch (Thursday Sep. 13, 2007)
  Impinj has said its multitime programmable memory has been fabricated in 65-nm process technology by foundry Taiwan Semiconductor Manufacturing Co. Ltd.
  
  
• VMETRO's Serial FPDP IP Core Supports Xilinx Virtex-5 FPGAs (Thursday Sep. 13, 2007)
  The Serial FPDP IP core is provided in either obfuscated source for simulation or in full VHDL source. Subject to licensing conditions, the core can also be used on non-VMETRO based Virtex-5, Virtex-4 and Virtex-II Pro based FPGA products.
  
  
• Evatronix USB subplatforms enable easy design-in of USB connectivity into System on Chips. (Wednesday Sep. 12, 2007)
  Evatronix today announced availability of its preintegrated USB solutions aimed at implementing applications using full speed (12 Mb/s) or high speed (480Mb/s) USB connections.
  
  
• Mixel Announces Two New PLLs Featuring Higher Performance, Reduced Power, Cost and Die Area (Tuesday Sep. 11, 2007)
  The High Performance Spread Spectrum Solution Offers Lower Integration Cost at Smaller Die Area, and the High Precision PLL Offers Higher Output Frequency Granularity, While Maintaining 50% Duty Cycle at Lower Power for Even and Odd Output Divisors
  
  
• S3 Delivers Another Industry First at 65nm - High Performance Mixed Signal Converter IP (Tuesday Sep. 11, 2007)
  S3 today announced the immediate availability of silicon results for its portfolio of high-performance, mixed-signal converter IP at the 65nm technology node. S3 is already delivering this IP to 2 of the top 10 global semiconductor companies.
  
  
• ARC Announces Ultra Low Power Technology "Energy PRO" That Lowers Core and Subsystem Power by Four Fold (Monday Sep. 10, 2007)
  Configurability enables creation of power efficient cores. Energy PRO further reduces power consumption by as much as four fold. ARC's new Energy PRO technology is supported by hardware and software solutions, and integrated with a new low power EDA flow and libraries that have been specifically optimized to Energy PRO.
  
  
• S1 Core updated to OpenSPARC T1 version 1.5 (Monday Sep. 10, 2007)
  One year after the first release, Simply RISC has updated the S1 Core design to make use of version 1.5 of the Verilog sources contained into the OpenSPARC T1 environment released by Sun Microsystems.
  
  
• Altera and PLDA Announce Audio Solution for Broadcast Market (Friday Sep. 07, 2007)
  Altera and PLDA SAS today announced an expanded collaboration to bring flexible solutions to the professional audio/video broadcast market. The initial result of this collaboration is the introduction of the first of a new line of intellectual property (IP) cores and the audio sample converter (SRC), which is now available free of IP license fees to qualified customers of Altera’s Stratix® and Cyclone® FPGA device families.
  
  
• Xilinx and MindWay Announce New Portfolio of Broadcast Modulation Solutions (Friday Sep. 07, 2007)
  The new IP cores support DVB-T/H, DVB-C, DVB-S and ATSC 8-VSB transmission standards, enabling design engineers to quickly adopt DVB technology in their design while drastically reducing overall system cost.
  
  
• Xilinx and intoPIX Team to Deliver Latest IP Solutions to Broadcast Industry (Friday Sep. 07, 2007)
  The intoPIX JPEG2000 encoding algorithm running on a Xilinx Virtex-5 FPGA, allows encoding at up to 120 frames-per-second (fps), over 20 percent faster than previous solutions. This creates the potential to create a multi-stream encoder delivering up to four channels of HD-SDI image management at 30 fps.
  
  
• Xilinx Announces High Definition Real-Time MPEG4 AVC/H.264 Encoder Solution (Friday Sep. 07, 2007)
  The solution is based on ATEME's high definition H.264 encoding platform, ideal for markets such as IPTV and satellite broadcast which require the best video quality at the lowest possible bit rates. The Virtex-5 FPGA based solution delivers the programmability and computing power required to deliver high definition video quality.
  
  
• Xilinx and Barco Announce Single-Chip JPEG2000 Implementation (Friday Sep. 07, 2007)
  Based on successful implementation of Barco Silex JPEG2000 cores on Xilinx® Virtex(TM)-5 FPGAs, the solutions significantly reduce the cost of broadcast and digital cinema initiative (DCI) archiving, post-production, distribution, and server systems.
  
  
• Mentor Graphics Offers PCI Express Controller and AMBA Bridge Intellectual Property Solutions (Wednesday Sep. 05, 2007)
  Mentor Graphics Corporation today announced availability of PCI Express® (PCIe®) Controller and AMBA® Bridge intellectual property (IP) solutions for the rapid and cost-effective integration into ASIC and System-On-Chip (SoC) platforms.
  
  
• Tensilica and Tallika Announce Secure SOC FPGA Platform (Wednesday Sep. 05, 2007)
  This fully verified and silicon proven hardware/software platform is ideal for any design team that needs a full implementation of RSA( including encryption, decryption, and key-pair generation acceleration) and/or an SOC with integrated hardware security functions.
  
  
• Faraday Implements 640 MHz ARM926EJ-S Hard Core Using UMC 90 nm Process Technology (Wednesday Sep. 05, 2007)
  Faraday's ARM926EJ-S™ hard core runs at 400 MHz under the worst case condition and could reach ultra high clock speed up to 640 MHz in a typical case with relatively low power consumption and small area. Currently the 90 nm hard core is ready, and its test chips will be available in October, 2007.
  
  
• Rambus and Cadence Collaborate and Deliver Fully Integrated and Independently Verified PCI Express Solutions (Tuesday Sep. 04, 2007)
  The two companies have collaborated and now offer highly adaptable PCI Express digital cores and PHY IP from Rambus, tightly integrated and verified with Cadence verification IP.
  
  
• Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000OCP for the Open Core Protocol 2.2 Interconnect (Monday Sep. 03, 2007)
  Specifically targeted for TFT LCD panels and the Open Core Protocol 2.2 On-Chip Interconnect, the DB9000OCP is an out-of-the-box synthesizable soft IP Core for ASIC and ASSP design teams with display system requirements.
  
  
• ASIC Architect Announces the Availability of AMBA 2 AHB to PCI Express Bridge (Wednesday Aug. 29, 2007)
  The solution product has passed PCI Express Compliance and Interoperability testing in PCI-SIG compliance workshop. This solution enables SoC designers to plug-in PCI Express Controller Core into AMBA 2 AHB system bus. This directly leads to low design implementation risk.
  
  
• Acacia Semiconductor Announces a New Family of Best-in-Class High-Speed 10-bit ADC IPs Silicon Proven in a 130nm Process (Tuesday Aug. 28, 2007)
  The new product family consists of six different ADC IPs that feature 10-bit resolution, single and dual channel solutions, sampling rates from 20MS/s up to 160MS/s and 300MHz sample-and-hold circuits.
  
  
• Kilopass Announces Embedded Non-Volatile Memory for 65 nm Low Power and 65 nm General Purpose Processes (Thursday Aug. 23, 2007)
  Kilopass XPM technology is the world’s first high-density embedded NVM technology verified in silicon and available for design in 65 nm standard logic CMOS processes. Kilopass is also making XPM-65LP and XPM-65G+ evaluation kits available to its customers.
  
  
• Salamander Error Correction announces 1 Gbps Viterbi decoder (Wednesday Aug. 22, 2007)
  Salamander Error Correction announced today the availability of the SALxx304d, a very high speed (1 Gbps) Viterbi decoder for telecommunications and high speed wireless networking applications.
  
  
• SNOWBUSH microelectronics Announces Silicon Verified 6-Bit, 2.5 GSPS, ADC IP Core in 90nm CMOS Process (Tuesday Aug. 21, 2007)
  SNOWBUSH's 6-bit ADC is compact, low-power, and by utilizing its high bandwidth sample-and-hold front-end, it maintains excellent dynamic performance throughout the full range of input frequencies. The ADC features INL of 0.59 LSB, DNL of 0.51 LSB, and ENOB of 5.2 or greater for sampling clock frequencies up to 2.5 GHz. The ADC occupies a silicon area of 0.43 square millimeters.
  
  
• Elliptic and Impinj Collaboration Bolsters System-On-Chip Digital Content Protection (Monday Aug. 20, 2007)
  Elliptic Semiconductor, Inc., and Impinj, Inc., today announced an agreement to collaboratively develop a secure, standards-based system-on-chip (SoC) reference architecture for content protection applications such as digital rights management (DRM) and conditional access. The reference architecture integrates Elliptic’s embedded security module (ESM) and Impinj’s AEON® multi-time programmable nonvolatile memory (NVM) core to counteract embedded system threats such as reverse chip engineering and cryptographic algorithm security breaches.
  
  
• Faraday Introduces Next Generation ARM v5 Compliant Ultra High Performance Processor - FA626TE (Tuesday Aug. 14, 2007)
  The first hard core which reaches the worst case clock speed at 533MHz is available in UMC 0.13um process. Faraday expects its next versions for 90nm in UMC, running 667MHz and 800MHz in worst case, to be available in initial Q4 and the end of 2007 respectively.