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IP / SOC Products News

• Synopsys and GLOBALFOUNDRIES Collaborate to Develop DesignWare IP for 22FDX Process (Wednesday Sep. 20, 2017)
  Synopsys today announced its collaboration with GLOBALFOUNDRIES (GF) to develop DesignWare® IP, including PHYs for USB 3.1/3.0/2.0, USB-C 3.1/DisplayPort, PCI Express® 3.1/2.0 and HDMI 2.0 TX, as well as data converters, for GF's 22FDX® process technology.
  
  
• Rambus Announces Industry's First Functional Silicon of Server DIMM Buffer Chipset Targeted for Next-generation DDR5 (Wednesday Sep. 20, 2017)
  Rambus today announced functional silicon of a double data rate (DDR) server DIMM (dual inline memory module) buffer chipset prototype for the next generation DDR5 memory technology.
  
  
• Synopsys Design Platform Certified by GLOBALFOUNDRIES for 22nm FD-SOI Process Technology (Wednesday Sep. 20, 2017)
  Synopsys today announced that GLOBALFOUNDRIES (GF) has certified the Synopsys Design Platform for the GF 22nm FD-SOI (22FDX™) process, ensuring designers achieve optimized implementation and predictable signoff results using industry leading digital design tools.
  
  
• Embedded FPGAs from Menta qualified for GLOBALFOUNDRIES' Advanced 14nm FinFET and 32nm SOI Process Technologies (Wednesday Sep. 20, 2017)
  Menta today announced that its embedded FPGA (eFPGA) IP is fully qualified for GLOBALFOUNDRIES’ (GF) advanced 14nm FinFET and 32nm SOI process technologies. Offered as part of GLOBALSOLUTIONS® Ecosystem, the eFPGA IP provides designers with a fully programmable FPGA fabric that can be embedded into any design.
  
  
• Synopsys' New ARC Secure IP Subsystem Addresses Security Threats in Embedded SIM and Other High-Value Embedded Applications (Tuesday Sep. 19, 2017)
  Synopsys, Inc. (Nasdaq: SNPS) today announced the new DesignWare® ARC® Secure IP Subsystem, an integrated, pre-verified hardware and software IP solution that addresses increasing security threats in high-value embedded applications such as embedded SIMs (eSIMs), smart metering and embedded Universal Integrated Circuit Cards (eUICC).
  
  
• Synopsys' New ARC IoT Development Kit Accelerates Software Development for Sensor Fusion, Voice Recognition and Face Detection Designs (Monday Sep. 18, 2017)
  Synopsys today announced the new DesignWare® ARC® IoT Development Kit to accelerate software development and debug of ARC processor-based system-on-chip (SoC) designs. The ARC IoT Development Kit includes a silicon implementation of the ARC Data Fusion IP Subsystem as well as a rich set of peripherals commonly used in IoT designs such as USB, I3C and PWM.
  
  
• PLDA Further Strengthen Partner Ecosystem, Unveils Comprehensive PCIe PHY and Controller integrated Solutions, to be Presented at IP-SoC China 2017 (Thursday Sep. 14, 2017)
  PLDA, the industry leader in PCI Express® interface IP solutions, today unveiled innovative PCIe PHY and PCIe Controller interop strategies that are ideally suited to ASIC and SoC designers developing PCIe-based designs.
  
  
• Synopsys and Alango Technologies Introduce Voice Enhancement Package Optimized for DesignWare ARC Data Fusion IP Subsystem (Wednesday Sep. 13, 2017)
  Synopsys and Alango Technologies today announced that Alango Technologies' Voice Enhancement Package (VEP) software has been optimized for Synopsys' DesignWare® ARC® Data Fusion IP Subsystem.
  
  
• Sidense and Intellitech collaborate on Electronic Chip IDs, anti-counterfeiting and semiconductor security for Secure Supply Chain Enablement (Tuesday Sep. 12, 2017)
  
  
  
• Mobiveil Inc. and Crossbar Inc. Announce Partnership to Apply Mobiveil's NVMe Solid State Drive IP to Crossbar's ReRAM IP blocks (Tuesday Sep. 12, 2017)
  Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (IP), platforms and IP-enabled design services and Crossbar, Inc., the ReRAM (Resistive Random Access Memory) technology leader, today announced a partnership to apply Mobiveil complete PCIe to NVMe set of solid state drive (SSD) IP to support the Crossbar, Inc., ReRAM IP blocks.
  
  
• Synopsys and TSMC Collaborate to Develop DesignWare Foundation IP for Low-Power TSMC 40-nm eFlash Processes (Tuesday Sep. 12, 2017)
  Synopsys today announced its collaboration with TSMC to develop foundry-sponsored DesignWare® Foundation IP, including logic libraries and embedded memories, for TSMC's 40-nanometer (nm) ultra-low power (ULP) eFlash and 40-nm low-power (LP) eFlash processes.
  
  
• Open-Silicon Completes Successful Silicon Validation of High Bandwidth Memory (HBM2) IP Subsystem Solution (Tuesday Sep. 12, 2017)
  Open-Silicon, a system-optimized ASIC solution provider, today announced it has successfully completed silicon validation of its High Bandwidth Memory (HBM2) IP subsystem in TSMC’s 16nm FinFET technology in combination with TSMC’s CoWoS® 2.5D silicon interposer technology and HBM2 memory.
  
  
• QuickLogic First to Offer eFPGA Technology on SMIC 40nm Low Leakage Process (Tuesday Sep. 12, 2017)
  QuickLogic's advanced architecture, mature software and IP ecosystem, in combination with the SMIC 40LL process, offers SoC designers an easy-to-implement, highly reliable and extremely low power eFPGA solution
  
  
• PathPartner Technology and Accelize Announce Availability of HEVC / H.265 FPGA Decoder for QuickPlay Development Platform (Monday Sep. 11, 2017)
  Pathpartner Technology, a leading provider of multimedia IP cores, software licensable modules and full-stack services, announces partnership with Accelize, a leading enabler of FPGA Acceleration-as-a-Service.
  
  
• Synopsys Successfully Tapes Out Broad IP Portfolio for TSMC 7-nm FinFET Process (Monday Sep. 11, 2017)
  Synopsys, Inc. (Nasdaq: SNPS) today announced the successful tape-out of a broad portfolio of DesignWare® Foundation and Interface PHY IP for TSMC's 7-nm process technology, including logic libraries, embedded memories, embedded test and repair, USB 3.1/2.0, USB-C 3.1/DisplayPort 1.4, DDR4/3, MIPI D-PHY, PCI Express® 4.0/3.1, Ethernet and SATA 6G.
  
  
• PLDA Announces Industry's First Controller for FPGA supporting PCIe 4.0 v0.9, Allowing immediate PCIe 4.0 implementation into FPGAs (Monday Sep. 11, 2017)
  PLDA today announced the availability of the industry’s first PCIe soft IP solutions to support PCIe® 4.0, rev 0.9 on FPGA. PLDA’s XpressRICH4™ and XpressRICH4-AXI™ IP solutions bring a track record of proven reliability, with many ASICs and SoCs already in production.
  
  
• Arastu Systems releases R-DIMM and LR-DIMM support for its DDR4 Controller (Friday Sep. 08, 2017)
  Arastu Systems’ DDR professionals, who carry the necessary wisdom required to traverse the DDR trajectory, have improvised DDR4 DRAM Memory Controller by adding support for Register Clock Driver (RCD) and Data Buffer (DB).
  
  
• Cadence Delivers Comprehensive IP Portfolio for TSMC 16FFC Automotive Design Enablement Platform (Thursday Sep. 07, 2017)
  Cadence Design Systems today announced it is delivering a comprehensive automotive IP portfolio for the TSMC 16nm FinFET Compact (16FFC) automotive process technology.
  
  
• Barco Silex integrates new video coding technique from the latest VC-2 HQ standard. (Thursday Sep. 07, 2017)
  Barco Silex has announced an upgraded version of its VC-2 HQ codec for high quality broadcast applications. This new version of our implementation of the codec is completely in-line with the recent update of VC-2 HQ open standard (SMPTE ST 2042-1:2017).
  
  
• SiFive and UltraSoC partner to accelerate RISC-V development through DesignShare (Thursday Sep. 07, 2017)
  SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative.
  
  
• Sital Technology and Logicircuit to Provide DO-254 Certified IP Cores for Avionic Data Buses (Thursday Sep. 07, 2017)
  Advanced data bus solutions provider Sital Technology, ltd. announces a new partnership with Logicircuit, Inc. and the resulting availability of DO-254 certified intellectual property (IP) cores for avionic products.
  
  
• Cadence Announces Legato Memory Solution, Industry's First Integrated Memory Design and Verification Solution (Thursday Sep. 07, 2017)
  Cadence today announced the Cadence® Legato™ Memory Solution, the industry’s first integrated solution for memory design and verification. The Legato Memory Solution eliminates the complexity of piecing together point tools for multiple design and verification tasks and can lead to productivity gains of up to 2X when compared with previous point tool offerings.
  
  
• Menta Embeds sureCore Low Power SRAM IP on TSMC's 28nm Process (Thursday Sep. 07, 2017)
  Menta SAS, a leading embedded FPGA (eFPGA) Intellectual Property (IP) provider, and sureCore Ltd., a low-power SRAM IP leader, today opened the doors to creative power-sensitive design in leading-edge applications with the availability of eFPGA IP with embedded sureCore PowerMiserTM low-power SRAM IP. The IP is optimized for the TSMC 28 nanometer process.
  
  
• Imec Reports World-Class Low-Power IP Blocks for 5G (Wednesday Sep. 06, 2017)
  Today, at its Imec Technology Forum Southeast Asia in Singapore, imec, the world-leading research and innovation hub in nano-electronics and digital technology, will present two key building blocks for future 5G applications featuring record low power consumption.
  
  
• Atomic Rules launches TimeServo System Timer IP Core for FPGA (Friday Sep. 01, 2017)
  Atomic Rules, a reconfigurable computing IP firm, is pleased to announce the launch of TimeServo, a Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component.
  
  
• Lattice Semiconductor Further Expands CrossLink Applications with Modular IP Cores (Tuesday Aug. 29, 2017)
  Lattice announces the availability of seven new modular IP cores for its award winning CrossLink FPGA product for increased design flexibility to support consumer, industrial and automotive applications.
  
  
• Synopsys Silicon-Proven DesignWare Bluetooth Low Energy Link Layer and PHY IP Achieve Bluetooth 5 Qualification (Tuesday Aug. 29, 2017)
  Synopsys, Inc. (Nasdaq: SNPS) today announced that the silicon-proven DesignWare® Bluetooth® Low Energy Link Layer IP and PHY IP in industry-standard 40-nanometer (nm) and 55-nm processes have achieved Bluetooth 5 qualification and have been declared compliant by the Bluetooth Special Interest Group.
  
  
• Rambus and Northwest Logic Certify Interoperability of HBM2 Interface Solution for High-performance Networking and Data Center Applications (Tuesday Aug. 29, 2017)
  Rambus, an innovator in semiconductor and IP products, today announced validated interoperability between its HBM2 PHY and Northwest Logics’ HBM2 Memory Controller Core.
  
  
• Moortec announce their Embedded In-Chip Monitoring Subsystem on TSMC 7FF (Wednesday Aug. 23, 2017)
  Moortec Semiconductor, specialists in embedded in-chip sensing, are pleased to announce the availability of their easy to integrate, embedded monitoring subsystem on TSMC’s 7nm FinFET (FF) process.
  
  
• Pinnacle Imaging Systems Launches Denali-MC HDR Image Signal Processor IP Core (Monday Aug. 21, 2017)
  Today, Pinnacle Imaging SystemsTM, announced the launch of its proprietary, Denali-MCTM camera-ready HDR Image Signal Processor (ISP) IP core. This next generation HDR video capture technology relies on Pinnacle Imaging’s advanced algorithms to accurately tone map high contrast scenes while minimizing HDR motion artifacts.