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frame buffer compression

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Frame buffer compression IP Listing

63 IP Cores (1 - 40)

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VESA DSC 1.2b Encoder for Xilinx FPGAs

VESA Display Stream Compression (DSC) 1.2b compliant ; Supports all DSC 1.2b mandatory and optional encoding mechanisms ; Backward compatible to DSC v1.1 ; Configurable maximum display resolution ...

1
VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs

VESA Display Stream Compression (DSC) 1.2b compliant ; Supports all DSC 1.2b mandatory and optional encoding mechanisms ; Backward compatible to DSC v1.1 ; Configurable maximum display resolution ...

2
Scalable UHD JPEG Encoder − Ultra-High Throughput, 8/10/12-bit per component and CBR video encoding

The UHT-JPEG-E core from Alma Technologies is a very high performance 8-bit Baseline and 12-bit Extended JPEG encoder, designed to enable the massive pixel rates of 4K & 8K UHD resolutions and ...

3
Display Controller IP

VeriSilicon's Vivante DC8000 Display Processing family is designed specifically for Wearable, MCU, MPU, and Mobile applications that need hardware UI displays and effects. It is absolutely essential ...

4
High-quality and powerful display processor

VeriSilicon's Vivante DC9000 Display Processing family is designed specifically for Mobile, Desktop, TV, and Projection applications that need powerful hardware UI displays, 8K ultra-high-resolution, ...

5
Baseline JPEG Encoder with optional Constant Bitrate Motion JPEG Video Rate Control

The JPEG-E core from Alma Technologies is a standalone and high-performance JPEG encoder for still image and video compression applications. Full compliance with the Baseline Sequential DCT ...

6
NTSC/PAL Adaptive 3D Comb Filter and Noise Reducer

Implemented in approximately 50,000 gates, the AVQ3000 is a silicon-efficient, high-quality solution for video decoding, noise reduction and video compression pre-processing. Using Adaptive ...

7
2D Compostion Processing IP

Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines them to create some of the most dynamic ...

8
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0

BODA955 is a full HD multi-standard video decoder IP for consumer multimedia products. This IP core is capable of decoding compressed video in a format of AVC/H.264 BP/MP/HP, VC-1 SP/MP/AP, ...

9
HEVC/H.265, H.264 and AVS2 Multi format Decoder IP for 4K 60fps

Chips&Media’s WAVE512 is one of the most advanced hardware video decoder IP core which supports the next generation HEVC(High-Efficiency Video Coding) standard known as H.265, AVC/H.264 and ...

10
HEVC/H.265, H.264, VP9 and AVS2 Multi format Decoder IP for 4K 60fps

Chips&Media’s WAVE515 is one of the most advanced hardware video decoder IP core which supports the next generation HEVC(High-Efficiency Video Coding) standard known as H.265, H.264, Google’s ...

11
HEVC/H.265, H.264 Multi format Decoder IP for 4K 60fps

Chips&Media WAVE511 is AVC.H.264 and HEVC/H.265 combined multi-standard video decoder IP, optimally designed with streamlined single-CORE to support 4Kp60. In recent days, the HEVC/H.265 ...

12
HEVC/H.265, H.264 Multi format Dual-core Codec IP for 8K 60fps

WAVE541C is a dual-CORE codec IP, optimally architected for real-time encoding or decoding video at 8K60 in HEVC/H.265 and AVC/H.264 video formats. This IP core provides high-performance encoding ...

13
UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading ...

14
Baseline JPEG Encoder Core

This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, ASIC or FPGA, hardware JPEG encoder ...

15
Baseline and Extended JPEG Encoder Core

This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, ASIC ...

16
Ultra-Fast Baseline and Extended JPEG Encoder Core

This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC ...

1 Testimonial
Masaitsu Nakajima, Head of Automotive Business Unit, Socionext

17
Motion JPEG Over IP - HD Video Encoder Subsystem

This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of complete motion JPEG video streaming products. Hardware reference designs ...

18
40G/50G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading ...

19
PowerVR Series8XE Graphics Processor

High-performance for entry-level markets The PowerVR Series8XE family of GPUs drives cost reduction in entry-level and mass market devices thanks to a design that has been optimised to deliver ...

20
PowerVR Series8XE Plus Graphics Processor

Series8XE Plus GPUs available in a range of configurations Available in two- and four-cluster configurations, Series8XE Plus is designed specifically to deliver the right mix of performance, ...

21
PowerVR Series8XT Graphics Processor

The PowerVR Series8XT family is based on the new Furian GPU Architecture and pushes mobile and embedded performance to new heights with configurations featuring 2 to 8 clusters offering dramatically ...

22
PowerVR Series9XE Graphic Processor

The PowerVR Series9XE family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter compression and the widely respected ...

23
PowerVR Series9XM Graphic Processor

The PowerVR Series9XM family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter compression and the widely respected ...

24
PowerVR Series9XE Graphic Processor

The PowerVR Series9XE family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter compression and the widely respected ...

25
PowerVR Series9XE Graphic Processor

The PowerVR Series9XE family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter compression and the widely respected ...

26
PowerVR Series9XE Graphic Processor

The PowerVR Series9XE family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter compression and the widely respected ...

27
PowerVR Series9XM Graphic Processor

The PowerVR Series9XM family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter compression and the widely respected ...

28
PowerVR Series9XM Graphic Processor

The PowerVR Series9XM family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter compression and the widely respected ...

29
PowerVR Series9XM Graphic Processor

The PowerVR Series9XM family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter compression and the widely respected ...

30
PowerVR Series8XT Graphics Processor

The PowerVR Series8XT family is based on the new Furian GPU Architecture and pushes mobile and embedded performance to new heights with configurations featuring 2 to 8 clusters offering dramatically ...

31
PowerVR Series8XE Plus Graphics Processor

Series8XE Plus GPUs available in a range of configurations Available in two- and four-cluster configurations, Series8XE Plus is designed specifically to deliver the right mix of performance, ...

32
PowerVR Series8XE Graphics Processor

High-performance for entry-level markets The PowerVR Series8XE family of GPUs drives cost reduction in entry-level and mass market devices thanks to a design that has been optimised to deliver ...

33
PowerVR Series8XE Graphics Processor

High-performance for entry-level markets The PowerVR Series8XE family of GPUs drives cost reduction in entry-level and mass market devices thanks to a design that has been optimised to deliver ...

34
PowerVR Series8XE Graphics Processor

High-performance for entry-level markets The PowerVR Series8XE family of GPUs drives cost reduction in entry-level and mass market devices thanks to a design that has been optimised to deliver ...

35
10/12-bit Extended & 8-bit Baseline JPEG Encoder with optional Constant Bitrate Motion JPEG Video Rate Control

The JPEG-E-X core from Alma Technologies is a standalone and high-performance 8-bit Baseline and 10/12-bit Extended JPEG encoder for still image and video compression applications. Full compliance ...

36
Display Controller - LCD / OLED Panels (AHB Bus)

The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel. In an ASSP, ASIC, or FPGA, typically, ...

37
Display Controller - LCD / OLED Panels (AXI Bus)

The Digital Blocks DB9000AXI LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a LCD or OLED display panel. ...

38
Display Controller - LCD / OLED Panels (AXI4 Bus)

The Digital Blocks DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protocol Interconnect to a LCD or OLED display panel. ...

39
CSIX to PI40

As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic managers (TM) and the switching fabric. The CSIX interface is designed ...

40

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