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Sata 3 IP Listing

160 IP Cores (1 - 40)

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Multi-protocol SerDes PMA

Multiprotocol SerDes PMA supporting variety of interfaces.

1 Testimonial
Lyle Smith, Vice President of Product Development Engineering, Microsemi SoC BU

1
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP

The PHY combo comprises Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification supporting PIPE interface ...

2
32G Multi Rate SerDes PHY - GlobalFoundries 22FDX

Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are ...

3
32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP

Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are ...

4
32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP

Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are ...

5
SATA 3 PHY

Gigacom's VSL340A PHY updated version of VSL340 to support SATA3 and backward compatible with SATA 1 and 2. VSL340A is suitable for both Host and Device applications within a Serial ATA system. ...

6
Serial ATA Gen 3 Host Controller (1.5, 3.0, 6.0 Gb/s)

The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential ...

7
Serial ATA Bridge Controller (1.5, 3.0, 6.0 Gb/s)

The Serial ATA Bridge IP Core provides an method to manipulate data between two SATA endpoints. High Performance, with maximum bandwidth data transfers.

8
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) 5th Generation

The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential ...

9
SATA/SAS 3.0 PHY

With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable ...

10
SATA Device IP Core (1.5, 3.0, 6.0 Gbps)

The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed ...

11
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) for Xilinx UltraScale

The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential ...

12
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)

The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential ...

13
Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC

The Multistandard SerDes is available in TSMC 65nm and GF28SLP process node to support wide range of standards like PCI, SATA, XFI etc.

14
Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP

Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SATA, XFI, USB, XAUI etc.

15
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP

Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SATA, XFI, USB, XAUI etc.

16
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP

Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SATA, XFI, USB, XAUI etc.

17
SATA III HOST Controller on Virtex 6

The SATA III HOST Controller IP Core incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The SATA III HOST Controller IP Core is compliant ...

18
SATA Host 6G Controller on Kintex 7

The SATA Host 6G Controller IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The SATA Host 6G Controller IP is compliant with Serial ...

19
SATA 3 Host Controller on ZYNQ

The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST XZ7 IP is compliant with Serial ATA III ...

20
SATA Device Controller on Kintex 7

The SATA Device IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The SATA Device IP is compliant with Serial ATA III specification ...

21
ZYNQ SATA 3 AHCI Host Controller with Linux Driver

The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS_SATA 3 HOST AHCI XZ7 ...

22
SATA 3 Host Controller on ARRIA V FPGA

The SATA 3 Host Controller IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA. The SATA 3 Host Controller IP is compliant ...

23
Virtex 7 GTX SATA 3 Host Controller

The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SATA 3 HOST XV7X IP is compliant with Serial ...

24
SATA HOST 3 ON VIRTEX 7 GTH

The LDS SATA 3 HOST XV7H IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTH speed grade 2 FPGA. The LDS SATA 3 HOST XV7H IP is compliant with Serial ...

25
SATA 3 Host Controller on Xilinx Artix 7

The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS_SATA3_HOST_XA7 IP is compliant with Serial ATA III ...

26
SATA HOST 3 ON KINTEX 7 Ultrascale

The LDS SATA 3 HOST XK7U IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 Ultrascale speed grade 2 FPGA. The LDS SATA 3 HOST XK7U IP is compliant with ...

27
SATA 3 HOST IP on ARRIA 10 FPGA

The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The LDS-SATA3-HOST-A10GX IP is compliant with ...

28
Xilinx Ultra Scale Plus SATA HOST IP

The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_HOST_GTHE4 IP is compliant with Serial ATA ...

29
SATA 3.0 PHY

The INNOSILICON mixed signal SATA3.0 transceiver PHY provides a complete SATA3.0 standard compliant transceiver physical interface solution for delivering high speed data over point to point ...

30
PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY

The Innosilicon PCIE3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for PCIE3.0 Super-Speed standard from Intel. ...

31
32G Multi-SerDes PHY

The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this particular datasheet, the PHY has been configured to support ...

32
25G Multi-SerDes PHY

The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet, the PHY has been configured to support ...

33
12.5G Multi-SerDes PHY

The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular datasheet, the PHY has been configured to ...

34
10G Multi-SerDes PHY

The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured to support a wide range of HS SERDES protocols ...

35
32G Multi-SerDes For PCIe5.0/USB3.x PHY

The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PHY has been configured to support PCIe5.0/USB3.x ...

36
5G Multi-SerDes For PCIe2.0/USB3.0 PHY

The Innosilicon 5Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 5Gbps within a single lane. For this datasheet, the PHY has been configured to support PCIe2.0/USB3.x ...

37
8G Multi-SerDes For PCIe3.0/USB3.0 PHY

The Innosilicon 8Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this datasheet, the PHY has been configured to support PCIe3.0/USB3.x ...

38
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process

Single channel serial ATA PHY layer compliant with SATA spec. of 3.0Gbps.

39
SATA 3.0 Host Controller

The SATA-HC IP block simplifies the integration of high capacity SSDs utilizing SATA I/II/III at 1.5/3/6Gbit/s data rates using Xilinx FPGAs. Combined low-latency and high throughput is achieved ...

40

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