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Today on Design-Reuse.com
CFX announces commercial availability of low cost automotive grade SonoS based charge trapping ...
Zhuhai Chuangfei Core Technology Co., Ltd. announced today that its latest developed high-reliability automotive-grade SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) ... Read
Qualitas Semiconductor expands presence in chinese market through strategic partnership with ...
Under the terms of the agreement, QUALITAS will provide an 8nm PCIe Gen 4 PHY IP license, empowering its Chinese partner to enhance networking chip design ... Read
AiM Future, a leading provider of concurrent multimodal inference accelerators for edge and endpoint devices, has just announced the launch of its next-generation ... Read
Partner Highlight
VeriSilicon today announced that Actions Technology (688049.SH), a low-power AIoT fabless semiconductor company, has adopted VeriSilicon’s power-efficient ... Read
Digital Core Design in cooperation with DCD-SEMI Unveils DCAN-XL: Revolutionary CAN XL IP ...
Designed to bridge the gap between CAN FD and 100Mbit Ethernet, the DCAN-XL sets a new standard in high-speed, reliable data transmission for automotive ... Read
Andes, HiRain, and HPMicro jointly announced that the three parties will cooperate to combine the AndesCoreTM RISC-V processor series, the HPMicro HPM6200 ... Read
Industry Expert Blogs
Rambus Blog 
Maven Silicon Blog By Sivakumar P R, Founder & CEO, Maven Silicon
EETimes Blog Timothy Chu, Managing Director, Accenture
Frontgrade Gaisler Blog Fabio Malatesta, Frontgrade Gaisler
Ethernet TSN Switch IP Core - Efficient and Massively Customizable ...
HBM3 PHY IP on TSMC N5
eDP 1.5 RX PHY on Samsung 14nm
DDR5 Registering Clock Driver (RCD) (DDR5RCD03)
16 bit, 5 Msps DAC in 12nm
CAN XL Controller
Capless LDO regulator in TSMC 22ULL 1.8V
High quality, low latency, secure video encoder for the transmission ...
32-bit CPU IP core supporting ISO 26262 ASIL B level functional ...
20 mA LDO voltage regulator (output voltage 1.1V/1.2V/1.3V/1.4V) ...
Cache MX, On-chip memory expansion
One Time Programmable IP on SMIC 55HV
Comprehensive, High Throughput Pixel Operation IP
SPMI Verification IP
BoW Verification IP
Simulation VIP for MIPI SoundWire-I3S
MIPI A-PHY Verification IP
UCIe Verification IP
Synthesizable DDR5 Bus Functional Model
SGPIO Verification IP
Integrated Droop Response System
Industry Articles
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Functional Safety for Control and Status Registers
Tim Schneider
Arteris -
An Introduction to Post-Quantum Cryptography Algorithms
Christos Kasparis
EnSilica -
The Rise of RISC-V and ISO 26262 Compliance
Simon Wang
Andes Technology -
Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)
Lakshmi Jain
Synopsys -
SoC NoCs: Homegrown or Commercial Off-the-Shelf?
Andy Nightingale
Arteris -
From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Vincenzo Liguori
Ocean Logic -
Embracing a More Secure Era with TLS 1.3
Lawrence Liu
PUFsecurity -
New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
Anton Shilov
