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Novas Extends Industry-Standard Debug Platform with Faster Performance and Advanced SystemVerilog Capabilities (Monday Jul. 09, 2007)
The Novas platform unifies the languages, abstractions and tools needed to cut in half the time it takes to understand and debug design behavior starting from system-level specification through silicon implementation. Novas' latest advancements are expected to deliver three to ten times more performance and capacity across the entire platform, and fuel adoption of SystemVerilog-driven verification methodologies with more automated debug solutions.
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Beach Solutions Ensures Higher Quality IP with Metric Driven Tool (Friday Jun. 29, 2007)
Beach Solutions EASI Tools Suite 3.8 Design Rule Checker Engine Now Includes More Checks, Graphical Output of Results and a 5x Speed Improvement Over Previous Releases
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Mentor Graphics Delivers Verification Solutions for ARM-based Wireless and Multimedia Applications (Tuesday Jun. 26, 2007)
Mentor's iSolve family of vertical market solutions now includes two new ARM processors, the ARM11 MPCore multiprocessor and the ARM1176JZF-S processor, adding to the existing iSolve portfolio of ARM7, ARM9 and ARM11 processors.
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Tensilica Enhances Reference Flow With Cadence Encounter RTL Compiler (Wednesday Jun. 20, 2007)
Encounter RTL Compiler with global synthesis enables Tensilica customers to achieve smaller, faster and lower-power implementations for microprocessor designs using Tensilica IP
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Synopsys Announces Virtual Platform for Marvell's PXA3xx Application Processors (Tuesday Jun. 19, 2007)
The DesignWare VPXA3 Virtual Platform provides software engineers with a high-speed, pre-silicon software execution environment that allows the development of system-on-chip- (SoC) related software before hardware is available. The Virtual Platform technology enables the creation of a software model of a complete system that fully mirrors the functionality of a complex, multicore hardware platform.
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EDA Leaders Team With MIPS Technologies to Support New High-performance MIPS32(R) 74K(TM) Core Family (Tuesday Jun. 05, 2007)
MIPS Technologies today announced that EDA industry leaders Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys, Inc. will team with the company to provide EDA software and tools support for its new high-performance MIPS32® 74K(TM) core family.
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MunEDA's tool family, WiCkeD, is selected by Faraday for its Analog IP Porting (Friday Jun. 01, 2007)
Faraday adopts powerful tools for the internal IP Porting and Technology Migration flow.
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Sonics and Synopsys Collaborate to Significantly Improve SoC SDRAM Memory Subsystem Performance (Thursday May. 31, 2007)
Sonics Announces New Version of MemMax(R) Memory Scheduler Enabling ''Plug and Play'' With Synopsys DDR2 SDRAM Protocol Controller IP
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Cadence and Denali Team Up to Enable Advanced DDR-PHY Methodology (Thursday May. 31, 2007)
Industry's Most Advanced DDR-PHY Solutions Achieved With Denali's Databahn PHY Architecture and CPF-Enabled Cadence SoC Encounter and Encounter Timing System
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Denali and Mentor Team Up to Enable Verification IP for SystemVerilog Verification Environments (Thursday May. 31, 2007)
Integration of PureSpec and AVM Ensures Availability of High-Quality Verification IP for Advanced SystemVerilog Verification
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Synopsys and ARM Optimize Reference Methodology for Aggressive Power Management (Tuesday May. 29, 2007)
Synopsys today announced an enhanced implementation Reference Methodology (iRM) for the ARM1176JZF-S synthesizable microprocessor that supports a wide array of aggressive power-management techniques.
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Legend releases Turbo-MSIM Fast-SPICE Simulator for Verification, Analysis and Characterization in SoC Design (Monday May. 28, 2007)
Turbo-MSIM can dramatically speed the time for simulating either full-chip hierarchical circuits or the flattened layout-extracted netlists with a huge number of resistors and capacitors.
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Yogitech Selects Mentor Graphics' Platform Express to Deliver IP-XACT Descriptions for Merchant IP Products (Tuesday May. 22, 2007)
At the request of a major customer, Yogitech decided to adopt the IP-XACT specification for its fRMEM products, a family of fault supervisors for memory sub-systems fulfilling the risk level SIL3 in accordance with IEC 61508 as certified by TÜV SÜD. Yogitech’s customer was already creating its designs using an IP-XACT design flow.
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Memory IP Characterization for 45nm Technology and below (Friday May. 18, 2007)
Address power-gating, data retention, pin power, multiple voltage supplies, ECSM/CCSM models, efficient layout extraction and circuit simulation.
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Duolog Technologies announces the release of BitWise, its powerful SPIRIT compliant register management tool (Thursday May. 17, 2007)
BitWise accelerates the SoC design flow by allowing SoC Design/Verification and SW engineering teams to collaborate early on. The communication mechanism is through common intersection areas of both disciplines; SoC registers and memory maps. BitWise is an integral part of the SOCRATES framework, an SoC/IP capture and integration platform which utilises the IP-XACT 1.2 standard of the SPIRIT Consortium.
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OneSpin Enhanced 360 Module Verifier Delivers Industry's Firt Complete Multi-Configuration IP Verification Solution (Monday May. 14, 2007)
The enhanced 360 MV supports the verification of IP with configurable functionality, such as optional memory-management units, or configurable synchronous or asynchronous FIFO implementations, and configurable dimensions, such as configurable bus-widths, FIFO depths, or register counts
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Cadence Speeds Adoption of Wireless and Consumer Low-power Designs with Low-power Methodology Kit (Monday May. 14, 2007)
The Cadence Low-Power Methodology Kit contains a generic wireless application design, implemented using multi-supply voltage and power shut-off methods, and all associated command scripts and technology files needed to carry the design through the entire end-to-end flow. The example IP in the design is from Cadence and third parties including ARM® processor and AMBA® on-chip communication technology, WiFi from Wipro, USB 2.0 from ChipIdea, 65-nanometer ultra low-power memories from Virage Logic and 65-nanometer technology libraries from TSMC.
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Leading Semiconductor Companies in China Adopt the VMM Verification Methodology (Monday May. 14, 2007)
Synopsys today announced that the VMM verification methodology, described in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog, has been adopted by major electronics companies in China for developing advanced verification environments
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Cadence Extends Verification Resources With New Plan-to-closure Methodology Qualified Program (Thursday May. 10, 2007)
Initial 22 Worldwide Partners Address Advanced Verification Planning and Management, Assertion-Based Verification, Reuse, and System-level Development
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Mentor Graphics Delivers Enhanced 0-In Clock Domain Crossing and Formal Verification Technology (Tuesday May. 08, 2007)
This new release includes significant technology enhancements allowing customers to apply advanced assertion-based verification techniques across a wider range of design types more efficiently. Specifically, the enhancements deliver increased performance and capacity to enable a more rapid means of finding and correcting critical bugs prior to committing designs to silicon.
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Dongbu HiTek adopts Legend Design Technology's Memory Characterization Tools for Quality Timing and Power Models (Monday May. 07, 2007)
Based upon layout-extracted circuit data with resistors and capacitors, Legend's CharFlo-Memory! toolset is able to generate accurate memory instance models of vendors' memory compilers at any PVT (process, voltage and temperature) corner. Dongbu HiTek chose Legend's CharFlo-Memory! as their standard memory characterization solution for quality timing and power models.
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Certess Launches Certitude, First Product to Enable the Functional Qualification of Electronic Designs (Monday May. 07, 2007)
ertitude certifies that if a semiconductor chip design had a bug, it would be found. It tackles the most formidable problem in functional verification: the absence of objective quality assurance in SoCs and IP blocks.
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IC Manage Announces Global Design Platform (GDP) for Scalable, Collaborative IC Design (Monday Apr. 23, 2007)
Utilizing the Perforce engine, IC Manage GDP also includes IT integration for hot backup, high availability, and disaster recovery for 24x7 enterprise availability, extending IC Manage's existing high performance revision control, configuration management and multi-site collaboration capabilities.
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GateRocket Delivers the EDA Industry's First Device Native Verification Solution for Advanced FPGAs (Monday Apr. 23, 2007)
RocketDriveTM is a hardware and software solution that adds significant value to existing design verification environments without a change in design flow or verification methodology.
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Satin IP Technologies committed to IP Reusability through the launch of VIP Lane, innovative Design-for-Reuse software cockpit (Wednesday Apr. 18, 2007)
VIP Lane is innovative Quality Management software supporting design engineers and project managers in their efforts to make Design-for-Reuse a daily reality.
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Magillem Design Services introduces MAGILLEM 4.0, the most comprehensive Integrated Design Environment based on the IP-XACT standards by The SPIRIT Consortium (Wednesday Apr. 18, 2007)
MAGILLEM, the pioneer tool suite, is a Database management system for the IP-XACT standards by the SPIRIT consortium™, and a complete design environment including debugging functions and the ability to run generators. MAGILLEM 4.0 offers an innovative tool for IPs Import and Packaging, Design Assembly and Flow Control.
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Mentor Graphics Launches Veloce Product Family Delivering Industry's Fastest Functional Verification Platform (Monday Apr. 16, 2007)
3-5X Productivity Boost for SoC and Embedded Systems Verification
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DOLPHIN Integration supports Lynguent for excellence in AMS modeling (Monday Apr. 09, 2007)
ModLyng will create models tuned for DOLPHIN Integration's single kernel SMASH for mixed signal simulation. Developers using SMASH will thus benefit from accelerated development schedules and expert feedback for improvements focused on behavioral simulation for AMS designers.
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ARM and Synplicity Announce Marketing and Collaboration Agreement for Cortex-M1 Processor (Tuesday Apr. 03, 2007)
Synplicity and ARM have announced a joint marketing and collaboration agreement which includes a reference methodology for the recently launched ARM Cortex-M1 processor – the first ARM processor specifically designed for implementation in FPGA
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Synopsys Accelerates Low-power Designs with Comprehensive Implementation and Verification Solution (Thursday Mar. 29, 2007)
Synopsys DesignWare® IP is architected for low power consumption in both active and standby modes. This is achieved by using power-efficient transmitters, phase-locked loop (PLL) blocks and clock gating techniques. Synopsys' USB 2.0 nanoPHY, designed for the latest mobility devices, consumes half the power of previous USB implementations. The PCI Express™, Serial ATA (SATA), and XAUI high-speed serializer/deserializer (SERDES) PHY IP support low-power modes and consume significantly less power than similar IP on the market.