Search for Silicon IP

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

Image processing specialized NPU

DDR5 PHY IP for TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps

13-bit, 80 MSPS Analog-to-Digital Converter IP Block

• 13-bit resolution
• 80 MSPS sampling speed
• Bandwidth: 2 MHz around Fs/4

MIPI CSI-2

• (SROI) Smart Region of Interest,
• (USL) Universal Serial Link,
• (AOSC) Always-On Sentinel Conduit,

DVB-S2X Wideband LDPC BCH Encoder IP Core

• Compliant with ETSI EN 302 307’
• Compliant with ETSI EN 302 307-2’
• Supports BCH-LDPC all code rates for digital video broadcasting

Register File with low power retention mode and 3 speed options

• Ultra-Low Leakage: High VT (HVT) and low leakage HVT (LLHVT) devices used with source biasing to minimize standby currents while operating at low voltage.

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP (8.0Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC

• Compatible with both C-PHY v2.1 and D-PHY v3.0 specifications for added flexibility.

PCIe 5.0 PHY IP for TSMC N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

5V Library for Generic I/O and ESD Applications TSMC 12nm FFC/FFC+ process.

• Targets up to 8A applications
• >8kV HBM
• Silicon Proven

8Kx8 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V Logic/BCD Process

• Fully compatible with MXIC 0.18µm BCD process
• High capacity: 64 kbits OTP macro
• Low voltage: 1.8 V ± 10% read and 3.70 V ± 5% program

12-bit, 5 GSPS ADC on GF 22FDX

• 12 bit resolution
• 5 GSPS sampling rate
• 6 GHz Input Bandwidth

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

Dilithium IP Core

• Supports sign and verify operations.
• Supports all three Dilithium modes.
• Has fully stallable input and output interfaces.

12-bit, 5 GSPS ADC on GF 22FDX

• 12 bit resolution
• 5 GSPS sampling rate
• 6 GHz Input Bandwidth

High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X

• Supports up to 9.6 Gbps/pin
• Supports 16 channels (32 pseudo channels)
• Supports AXI4 mainband and AXI4-Lite sideband interfaces

DiFi IP core

• Supports: Signal Data, Flow Control, Signal and Version Context Packets
• Integrates Easily with UDP/IP Ethernet Stack through the AXI interface

PCIe GEN6 PHY

• Supports PRBS (Pseudo Random Binary Sequence) testing including loopback modes

DDR4 Memory Controller

Universal Chiplet Interconnect Express (UCIe) Controller

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

HBM3 PHY & Controller

• One stop PHY & Controller solution with an average random efficiency of more than 85%
• Supports up to 6400 MT/s

32G Multi-SerDes PHY

112G Ethernet PHY IP LR-Max for TSMC N4P

• Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)