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New Silicon IP
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CAN XL Controller
- Designed in accordance with ISO 11898‐1:2024 specification (tbc) and CiA610-1 specification
- Supports CAN, CAN FD and CAN-XL frames
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Capless LDO regulator in TSMC 22ULL 1.8V
- Low silicon area
- Fast transient response
- Low-Power (LP) mode to supply AON domain
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High quality, low latency, secure video encoder for the transmission of HD video
- Supports all SMPTE non-interlaced standards from 720p/23 to 1080p/60.
- Supports YCbCr or RAW data formats.
- Can interface directly to image sensor.
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PCIe 6.0 PHY IP for TSMC N3E
- Supports the latest features of PCIe 6.0 specification
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- Certified according to ISO 26262:2018 edition series of standards
- RISC-V RV32GCBP Instructions
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20 mA LDO voltage regulator (output voltage 1.1V/1.2V/1.3V/1.4V)
- TSMC EF CMOS 55nm
- High precision stabilization voltage
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On-chip memory expansion
- On-the-fly compression / decompression of cache lines
- Optional secureTraining on metadata capability
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OTP One Time Programmable IP SMIC 55HV
- Small IP Size
- High reliability
- Radiation hardening
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MIPI C-PHY v2.0 D-PHY v2.1 for TSMC N5A
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
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Comprehensive, High Throughput Pixel Operation IP
- Memory to Memory IP
- Diverse Input/Output Formats
- Rich Pixel Processing Functions
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32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
- Ideal either as a Main Controller or a Safety Island in a Functional Safety System
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Securyzr™ Intrusion Detection System (IDS)
- Part of a global threat detection, analysis and response solution form Chip-to-Cloud relying on Securyzr™ iSSP (integrated Security Services Platform).
Top Silicon IP
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1
RISC-V GPGPU for 3D graphics and AI at the edge
- Unparalleled RISC-V flexibility & programmability
- Compelling ultra-low power 3D for wearables & aiot
- Enabling your ai application without additional silicon cost
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32-Bit RISC-V Embedded Processor and Subsystem. Maps ARM M-0 to M-4. Optimal PPA.
- 32-bit RISC-V core
- 2-stage pipeline
- Available in many versions
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3
High-Density eMRAM Compiler TSMC 22ULL
- eMRAM compiler enabling low-power designs requiring high memory capacity
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4
High Image Quality Super Resolution IP
- Up to 8K @ 60 FPS
- Up to 4 pixels per clock
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5
Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
- Drag & Drop Graphical User Interface
- Unified configuration tree view
- Intelligent routing path calculation
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6
Ultra low power AI inference accelerator
- Energy Efficient
- High Performance
- Small footprint
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7
General Purpose Neural Processing Unit (NPU)
- Hybrid Von Neuman + 2D SIMD matrix architecture
- 64b Instruction word, single instruction issue per clock
- 7-stage, in-order pipeline
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Highly scalable inference NPU IP for next-gen AI applications
- Matrix Multiplication: 4096 MACs/cycles (int 8), 1024 MACs/cycles (int 16)
- Vector processor: RISC-V with RVV 1.0
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9
GDDR7 Memory Controller
- Up to 40 Gbps per pin operation
- Optimized for high efficiency and low latency across a wide variety of traffic scenarios
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10
32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
- Ideal either as a Main Controller or a Safety Island in a Functional Safety System
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High speed NoC (Network On-Chip) Interconnect IP
- High Performance
- Low Power Consumption
- Smaller Area
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64-bit RISC-V Application Processor Core
- 64-bit RISC-V core
- Linux capable
- In-order 7-stage pipeline
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