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axi to apb bus bridge

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Axi to apb bus bridge IP Listing

33 IP Cores

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AXI to APB Bus Bridge

The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one governing the AXI transactions, and one ...

1
AXI to APB Bridge

The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly configurable core translates read or write ...

2
AXI to APB Bridge

The AXI (Advanced eXtensible Interface) to APB (Advanced Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions. It functions as a slave on the AXI4-Lite interface and ...

3
AXI2APB bridge

Vtool AXI2APB bridge establishes communication between AXI master and configurable number of APB slaves translating AXI to APB transactions and providing synchronization block between fast (AXI) ...

4
I2C Slave with APB Master Bridge (I2C2APB)

The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

5
I2C Slave with AXI Master Bridge (I2C2AXI4)

The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

6
Bus Bridges

Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely and without loss of data. SOC is essentially a system made up ...

7
APB Subsystem

The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem is ready for integration with processors ...

8
AXI Subsystem

The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces such as the BA20, BA21, and several RISC-V ...

9
I2C Slave To AXI Bridge IP

I2C Slave To AXI Bridge interface provides full support for the two-wire I2C synchronous serial interface, compatible with I2C version 6.0 specification. Through its I2C compatibility, it provides ...

10
MIPI I3C Slave To AXI Bridge IP

MIPI I3C Slave To AXI Bridge interface provides full support for the two-wire MIPI I3C synchronous serial interface, compatible with MIPI I3C version 2.0 standard.Through its MIPI I3C compatibility, ...

11
SPI Slave To AXI Bridge IP

SPI Slave To AXI Bridge interface provides full support for the two-wire SPI synchronous serial interface, compatible with SPI version Block Guide 4.01 standard. Through its SPI compatibility, ...

12
MIPI SPMI Slave AXI Bridge IP

MIPI SPMI Slave AXI Bridge interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI compatibility, it provides ...

13
AXI SRAM Bridge

AXI4 to memory bridge with SECDEC and exclusive access support axi2mem bridge should be used to connect standard RAM or ROM blocks with plain CE-WE input control interface to AXI4 bus. It ...

14
I2C Slave with AHB Master Bridge (I2C2AHB)

The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

15
AHB-Lite to AHB-Lite Asynchronous Bridge

The AHB-Lite to AHB-Lite Asynchronous Bridge translates an AHB-Lite bus transaction (read or write) on one clock domain to an AHB-Lite bus transaction on a second (asynchronous) clock domain. ...

16
Advanced Encryption Standard compliant with FIPS 197

AES bridge, a cryptographic coprocessor that complies with FIPS 197 Advanced Encryption Standard, employs the Rijndael encryption method to link APB, AHB, and AXI bus. AES is a block cipher ...

17
AHB Quad SPI Controller with Execute in Place

The Quad Serial Peripheral Interface (OSPI) core is a serial data link (SPI) master which controls an external serial FLASH device. Reading and writing the core is done on the AMBA® AHB ...

18
LIN Bus Controller – Basic and Safety-Enhanced

DCD-SEMI believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That’s why our DLIN controller with UART half-duplex enhanced ...

2 Testimonials
Alex Chen, Project Leader of Business Project Department, Faraday Technology Corporation

19
AXI4 to/from Stream DMA

The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals and a memory-mapped AXI4 bus. The core implements two independent ...

20
AXI Performance Subsystem

The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance. This system contains an 8 master, 16 slave ...

21
MIPI I3C Slave To AHB Bridge IP

MIPI I3C Slave To AHB Bridge interface provides full support for the two-wire MIPI I3C synchronous serial interface, compatible with MIPI I3C specification version 2.0. Through its MIPI I3C ...

22
I2C Slave To AHB Bridge IP

I2C Slave To AHB Bridge interface provides full support for the two-wire I2C synchronous serial interface, compatible with I2C version 6.0 specification. Through its I2C compatibility, it provides ...

23
SPI Slave To AHB Bridge IP

SPI Slave To AHB Bridge interface provides full support for the two-wire SPI synchronous serial interface, compatible with SPI version Block Guide 4.01 standard. Through its SPI compatibility, ...

24
SPI Slave To SOC Bridge IP

SPI Slave To SOC Bridge interface provides full support for the two-wire SPI synchronous serial interface, compatible with SPI version Block Guide 4.01 standard. Through its SPI compatibility, ...

25
AHB2APB Bridge IP

Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency, power, and area

26
Secure Hash Algorithm 384 IP Core

Bridge to APB, AHB, and AXI bus SHA2-384 is a universal solution that effectively speeds up the SHA2-384 hash function that complies with FIPS PUB 180-4. It has three options for computing message ...

27
Secure Hash Algorithm 512 IP Core

A universal solution that effectively accelerates the SHA2-512 hash function complying with FIPS PUB 180-4 is the SHA2-512 bridge to APB, AHB, and AXI bus. It computes the message digest in ...

28
Secure Hash Algorithm 256 IP Core

A universal solution that effectively accelerates the SHA2-256 hash function conforming with FIPS PUB 180-4 is the SHA2-256 bridge to APB, AHB, and AXI bus. It has two modes for computing message ...

29
TSN Ethernet Switched Endpoint Controller

The TSN-SE implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware ...

30
MACsec Protocol Engine for 10/100/1000 Ethernet

The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports all cipher suites provisioned by the MACsec standard ...

31
UART Core with SDLC Function

D8530 bridge to APB, AHB, and AXI bus, it is a dual-channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device, designed for use with 8 and 16-bit microprocessors. It works ...

32
Hash and HMAC Functions Accelerator

The DSHA2-384 - a universal solution that accelerates SHA2-384 hash with HMAC mode. DSHA2-384 bridge to APB, AHB, AXI bus, it is a universal solution that efficiently accelerates SHA2-384 ...

33

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