Jul. 09, 2007 - OCP-IP today announced their support of Cadence’s Assertion Based Verification IP (ABVIP) for the development and verification of the OCP protocol. OCP’s ascendance as the system architecture “backbone” within increasingly complex consumer and portable designs has driven the need for improved ...

Jun. 28, 2007 - Synopsys today announced that it has teamed with UMC to port the Synopsys DesignWare USB 2.0, PCI Express, SATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90-nanometer (nm) and 65-nm technologies

Jun. 20, 2007 - Encounter RTL Compiler with global synthesis enables Tensilica customers to achieve smaller, faster and lower-power implementations for microprocessor designs using Tensilica IP

Jun. 19, 2007 - The DesignWare VPXA3 Virtual Platform provides software engineers with a high-speed, pre-silicon software execution environment that allows the development of system-on-chip- (SoC) related software before hardware is available. The Virtual Platform technology enables the creation of a software model ...

Jun. 18, 2007 - Recognizing the semiconductor industry's need for an open market approach to providing comprehensive analog intellectual property (IP) solutions, Chipidea®, the world leader in analog/mixed-signal subsystems and IP, today announced it has created the first Analog IP Foundry(TM) to help customers circumvent ...

Jun. 12, 2007 - Chartered Semiconductor Manufacturing and Tezzaron Semiconductor today announced that Chartered is beginning to ramp production of Tezzaron's unique ultra high-speed memory chips.

Jun. 14, 2007 - With the complexity of both hardware and software growing significantly, the challenge of designing and testing software earlier in the design process is becoming an increasingly significant factor, especially in cases where the hardware environment may be extremely complex and/or not yet available.

Jun. 06, 2007 - The KAIST (Korea Advanced Institute of Science and Technology) has licensed the Xtensa configurable processor to develop multimedia SOC (system-on-chip) designs.

Jun. 05, 2007 - Focusing on the methodology described in the Verification Methodology Manual (VMM) for SystemVerilog book, the VMM Catalyst Program is open to electronic design automation (EDA) vendors, silicon and verification intellectual property (IP) companies, and training and service providers to benefit mutual ...

Jun. 04, 2007 - This is the second node, following 65nm, where the alliance partners have driven comprehensive DFM solutions, which marry technology and tool support from leading EDA and DFM suppliers with manufacturing data and models from the Common Platform technology foundries to help ensure the success of chip ...

Jun. 04, 2007 - Adaptive Verification IP combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually. Adaptive Verification IP complements existing random or directed-random methods with a powerful new approach ...

Jun. 04, 2007 - Reference Flow 8.0 supports TSMC's 45nm process technology with advanced standard cell, standard I/O, and SRAM compiler. Key features address new design challenges at 45nm, including statistical timing analysis for intra-die variation, automated DFM hot-spot fixing, and new dynamic low-power design ...

Jun. 01, 2007 - Lightspeed Logic today announced immediate availability of the 65-nanometer Common Power Format (CPF)-enabled reference flow for Lightspeed Logic’s Reconfigurable Logic IP. This reference flow enables SOC designers to accelerate time-to-market for low-power designs using Lightspeed Logic’s Reconfigurable ...

May. 31, 2007 - The kits have been validated and are available now for use with Mentor Graphics ICstudio design platform. These open-source design kits enable IC design companies to rapidly set up their design environments and immediately focus on mixed-signal design and productivity gains on leading-edge technology ...

May. 31, 2007 - Integration of PureSpec and AVM Ensures Availability of High-Quality Verification IP for Advanced SystemVerilog Verification

May. 31, 2007 - Industry's Most Advanced DDR-PHY Solutions Achieved With Denali's Databahn PHY Architecture and CPF-Enabled Cadence SoC Encounter and Encounter Timing System

May. 30, 2007 - BDTI has released independent benchmark results for the Cortex-A8, ARM's highest-performance processor core, on the BDTI DSP Kernel Benchmarks and the BDTI Video Encoder and Decoder Benchmarks. The results indicate that the Cortex-A8 is significantly faster than its predecessor, the ARM1176, giving ...

May. 25, 2007 - DAFCA's ClearBlue(TM) Reconfigurable Instrumentation IP and Software accelerated "silicon bring-up" schedules at Infineon

May. 24, 2007 - With 112 GMACs, Storm-1 SP16HP offers a cost-effective, easy-to-design, C-programmable alternative to FPGA and multi-DSP designs

May. 17, 2007 - The DesignWare Switch IP for PCI Express is used to power Agilent Technologies' Protocol Test Card (PTC), one of three ''Gold Tests'' required by PCI-SIG for products to achieve compliance and be listed on PCI-SIG's Integrators List.

May. 17, 2007 - The company's programmable coprocessor methodology enables multicore platform design while eliminating the need to redevelop applications software to use multiple threads, a time-consuming task with testability and reliability challenges and difficult-to-predict performance outcomes.

May. 14, 2007 - The Cadence Low-Power Methodology Kit contains a generic wireless application design, implemented using multi-supply voltage and power shut-off methods, and all associated command scripts and technology files needed to carry the design through the entire end-to-end flow. The example IP in the design ...

May. 14, 2007 - Synopsys today announced that the VMM verification methodology, described in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog, has been adopted by major electronics companies in China for developing advanced verification environments

May. 10, 2007 - Initial 22 Worldwide Partners Address Advanced Verification Planning and Management, Assertion-Based Verification, Reuse, and System-level Development

May. 09, 2007 - Lightspeed Logic's Reconfigurable Logic delivers a density and performance breakthrough for mask reconfigurable solutions, achieving 80% the density of traditional methodologies for multi-million gate logic blocks, twice the density of competing mask reconfigurable solutions.

May. 07, 2007 - ertitude certifies that if a semiconductor chip design had a bug, it would be found. It tackles the most formidable problem in functional verification: the absence of objective quality assurance in SoCs and IP blocks.

Apr. 20, 2007 - The demand for analog/mixed-signal intellectual property (IP) blocks has never been greater, especially at the 65-nm process node and below.

Apr. 20, 2007 - This successful tape-out marks the first of four 65 nm tape-outs planned by GUC in the first half of 2007. The company is also planningtwo testchip tape-outs in 45nm before the end of 2007. Additionally, projects using GUC's 90nm process will begin mass production later this year.

Apr. 17, 2007 - The partnership expands the customer support for Rambus intellectual property (IP) through TES' extensive network of worldwide design centers. Under the agreement, TES will market and integrate Rambus IP products as part of its IC and system designs.

Apr. 17, 2007 - The Open SystemCT Initiative (OSCI) released a new report today confirming worldwide adoption of SystemC is strong and continues to grow, and that SystemC user groups in all geographies are quickly adding members and taking an active role in promoting standardization efforts.

Apr. 13, 2007 - As part of the realignment, Kay Chai ''KC'' Ang becomes senior vice president of worldwide sales and marketing, and Dr. Simon Yang assumes the duties of senior vice president of fab operations, in addition to his current role as chief technology officer (CTO). Mike Rekuc becomes president of the Americas ...

Apr. 10, 2007 - Lightspeed Logic provides mask reconfigurable IP, a digital logic implementation technology that provides time-to-market, yield, manufacturability, and development expense advantages over standard-cell implementation. Clear Shape and Lightspeed will collaborate to verify the manufacturability of Lightspeed's ...

Apr. 10, 2007 - Synopsys and OCP-IP today announced that they are collaborating to provide Synopsys' DesignWare(R) Verification IP (VIP) as part of OCP-IP's CoreCreator verification toolset.

Mar. 29, 2007 - Synopsys DesignWare® IP is architected for low power consumption in both active and standby modes. This is achieved by using power-efficient transmitters, phase-locked loop (PLL) blocks and clock gating techniques. Synopsys' USB 2.0 nanoPHY, designed for the latest mobility devices, consumes half the ...

Mar. 28, 2007 - The Galaxy™ Design Platform RTL-to-GDSII flow for the synthesizable ARM® Cortex™-A8 processor includes DC Topographical technology, the DFT MAX solution and the latest physical design technology available in IC Compiler.

Mar. 12, 2007 - With backing from Index Ventures, Certess' mission is to develop breakthrough technology to perform ''functional qualification,'' providing verification engineers with the ability to tell if design errors could go undetected and enabling the objective evaluation of the quality of the functional verification, ...

Feb. 22, 2007 - Led by general manager Fabrice Jovenin and initially staffed by 12 RF and analog engineers, the company's new design center will be focused on the research and development of advanced RF technology at 90nm and 65nm

Feb. 20, 2007 - Denali's Databahn solutions help GUC's developers quickly configure high-speed DDR2 and mobile DDR memory systems that meet or exceed customer design requirements in terms of bandwidth, latency and power reduction.

Feb. 14, 2007 - The DesignWare digital controller IP for PCI Express 2.0 is fully compliant with the recently released PCI Express 2.0 specification and has successfully passed the latest PCI Express compliance testing at the PCI-SIG interoperability workshop held in the United States in December 2006.

Feb. 12, 2007 - Targets growth at 50% in 2007; To recruit 300 engineering professionals in 2007; New centre to focus on chip design & multimedia applications