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Jun. 13, 2005 -
The intellectual property (IP) market — as it refers to predefined circuit blocks — is far from dead and is becoming more diverse through the rise of vendors of analog and mixed-signal IP, according to Christian Heidarson, an analyst with Gartner Inc., sp
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Jun. 09, 2005 -
The chip, in development for the past 12 months with a team of up to twenty S3 engineers, includes a complex DRAM arbitration system, a microprocessor, embedded memories, connectivity peripherals and proprietary customer application-specific functional mo
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Jun. 08, 2005 -
As part of the agreement, S3 designed and delivered a complete Analog Front-End (AFE) that included a range of S3's silicon-proven, mixed signal IP supported by extensive integration consultancy from S3's experienced mixed signal designers
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Jun. 06, 2005 -
Industry’s first third-party low-power IP available for a foundry 65nm process
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May. 31, 2005 -
AccelChip Focuses on DSP Solutions in Booth 1000
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May. 30, 2005 -
Chartered Names Dr. Liang Choo Hsia as SVP Technology Development
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May. 31, 2005 -
Pistorio brings to Chartered more than 38 years of industry leadership experience
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May. 30, 2005 -
Dr. Hsia joined Chartered in 2000 as vice president for advanced module development and has been leading Chartered's joint development efforts with IBM at 90 nanometer (nm) as well as 65nm development with IBM, Infineon and Samsung
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May. 25, 2005 -
Addition of low-power library, reference flows, and critical cores enhances sourcing flexibility for leading-edge 90nm designs
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May. 25, 2005 -
Companies extend relationship to offer foundry customers sophisticated, low-power design techniques and high-speed connectivity solutions
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May. 24, 2005 -
Customers to have download access to IP via ARM website at no charge
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May. 23, 2005 -
ESL Now! Companies Invite Electronics Designers to Participate in Survey on www.esl-now.com and be Entered to Win a Sony PSP
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May. 23, 2005 -
New service leverages 500+ man-years of expertise in designing and verifying complex chips
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May. 19, 2005 -
Flexible Wafer-level Packaging Methodology Allows Same Silicon Design to Be Offered in Wire-bond or Flip-chip Bump Interconnect Format
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May. 13, 2005 -
Worldwide merchant market dollar shipments of structured ASIC products are forecast to soar from the $209.8 million reached last year to $2.53 billion by 2009, reports In-Stat (http://www.in-stat.com)
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May. 10, 2005 -
The CheckerWare solution is comprised of a library exceeding 100 assertion checkers and protocol monitors, making possible the quick adoption of cutting edge assertion-based and formal verification methodologies without the cost and risk often associated
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Mar. 30, 2005 -
The 2003 International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design productivity improvement will come from IP reuse and 25 percent from improved EDA tools, flow, or methodologies
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Apr. 27, 2005 -
The new release features enhanced capabilities for solving implementation challenges inherent in state-of-the-art algorithms found in multimedia (H.264, WMV), imaging (photo-quality printing), wireless (3GPP), and security (AES) applications. PICO Expres
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Apr. 20, 2005 -
sci-worx to Use Tensilica Xtensa LX Processors As Building Blocks for Next Generation Video Cores
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Apr. 18, 2005 -
Cutting a fast path to semiconductors: With special synthesis and processing, algorithms turn into silicon-but keep an eye on hardware
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Apr. 18, 2005 -
Foundries should drive IP quality
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Apr. 14, 2005 -
Mentor VP highlights growing need for systems design reuse
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Apr. 12, 2005 -
Silicon & Software Systems (S3) honored as a key contributor to Award Winning Medical Product Design
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Apr. 11, 2005 -
LSI Logic Receives Industry's First Qml Certification at 0.13-Micron for Military and Aerospace Applications
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Apr. 04, 2005 -
IP analysis firm eyes Russia through outsource pact
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Apr. 07, 2005 -
IBM exec calls for system-level tools
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Apr. 06, 2005 -
UpZide and Tensilica to Cooperate on VDSL2 Data-Path Design
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Apr. 04, 2005 -
Agilent Technologies Uses Zenasis Technologies' ZenTime to Increase System-on-Chip Performance and Accelerate Time to Silicon
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Mar. 30, 2005 -
ZAiQ Technologies and S2C Inc. Collaborate on a Transaction-Based SoC Design and Validation System
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Mar. 28, 2005 -
Chartered Details Comprehensive Market-Specific Solutions for High-Volume Consumer and Wireless Products
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Mar. 22, 2005 -
Proactive approach needed to overcome 90-nm quality challenges, experts say
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Mar. 23, 2005 -
TSMC exec calls for proactive measures on IP
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Mar. 21, 2005 -
Silicon Design Chain Collaboration Demonstrates Significant 90-nanometer Total Power reduction; Applied Materials, ARM, Cadence and TSMC Integrated Capabilities Deliver Silicon-Validated Power Reduction
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Mar. 14, 2005 -
ZAiQ Technologies and ProDesign Integrate High Speed Transaction-Based Verification System
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Mar. 14, 2005 -
Arteris introduces industry's first products for building networks on Chip (NoC)
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Mar. 08, 2005 -
Chipidea, Solid Silicon Technology Offer Integrated USB 2.0 and USB 2.0 OTG IP Solutions for Chartered's 0.13-Micron and 0.18-Micron Processes
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Mar. 04, 2005 -
Chartered updates guidance for first quarter
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Feb. 28, 2005 -
Chartered Provides Early Access to Design-Ready 65-Nanometer Process Platform for 300mm Manufacturing
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Feb. 28, 2005 -
ARM and Synopsys Announce Industry-First and Recommended Flow For ARM11 Family With Intelligent Energy Manager Technology
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Mar. 01, 2005 -
ESL Design State of the Union 2005