The INNOSILICON 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32G Gbps within a single lane. For this particular databook, the PHY has been configured to support HMC-30G-VSR specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.