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Ddr IP Listing

1021 IP Cores (1 - 40)

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DDR 4/3/3L 3200 HS PHY TSMC 16FFLL+

The Cadence Denali High-Speed DDR PHY IP supports DDR4/DDR3/DDR3L, provides low latency, and enables up to 3200Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer ...

1
DDR 4/3/3L 3200 HS PHY TSMC 16FFGL+

The Cadence Denali High-Speed DDR PHY IP supports DDR4/DDR3/DDR3L, provides low latency, and enables up to 3200Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer ...

2
DDR 4/3/3L 2400 HS PHY TSMC 28HPM

The Cadence Denali High-Speed DDR PHY IP supports DDR4/DDR3/DDR3L, provides low latency, and enables up to 2400Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer ...

3
DDR 4/3/3L 2400 HS PHY TSMC 28HPC

The Cadence Denali High-Speed DDR PHY IP supports DDR4/DDR3/DDR3L, provides low latency, and enables up to 2400Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer ...

4
LPDDR 4/3 DDR 4/3/3L 2400 PHY TSMC 28HPM

The Cadence Denali DDR PHY IP supports DDR4/DDR3/DDR3L/LPDDR4/LPDDR3, provides low latency, and enables up to 2400Mbps throughput and bandwidth necessary for today s mobile, enterprise, and ...

5
LPDDR 4/3 DDR 4/3/3L 2400 PHY TSMC 28HPC

The Cadence Denali DDR PHY IP supports DDR4/DDR3/DDR3L/LPDDR4/LPDDR3, provides low latency, and enables up to 2400Mbps throughput and bandwidth necessary for today s mobile, enterprise, and ...

6
LPDDR 3/2 DDR 3/3L 1600 PHY TSMC 40LP

The Cadence Denali DDR PHY IP supports DDR4/DDR3/DDR3L/LPDDR4/LPDDR3, provides low latency, and enables 1600Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer ...

7
DDR 4/3 2400 HS PHY GF28HPP

The Cadence Denali High-Speed DDR PHY IP supports DDR4/DDR3, provides low latency, and enables up to 2400Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer ...

8
LPDDR 3/2 DDR 3/3L 1600 PHY GF 28SLP

The Cadence Denali DDR PHY IP supports DDR3/DDR3L/LPDDR3/LPDDR2, provides low latency, and enables 1600Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer applications, ...

9
LPDDR 3/2 DDR 3/3L 1600 PHY SMIC 28HK

The Cadence Denali DDR PHY IP supports DDR3/DDR3L/LPDDR3/LPDDR2, provides low latency, and enables 1600Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer applications, ...

10
TSMC CLN28HPM 28nm DDR 4/3 PHY - 3200Mbps

The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. ...

11
TSMC CLN7FF 7nm DDR DLL - 250MHz-1250MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

12
TSMC CLN7FFLVT 7nm DDR DLL - 360MHz-1800MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

13
TSMC CLN28HPC+ 28nm DDR 4/3 PHY - 3200Mbps

The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. ...

14
Fractional-N Frequency Synthesizer PLL (5nm - 180nm)

Widely programmable fractional-N delta sigma frequency synthesizer. Low Power/ Low Area hard macro with industry leading jitter performance for its power/area class. Product is currently ...

1 Testimonial
Kazuhisa Sasaki, General Manager, Development Department, THine Electronics, Inc.

15
TSMC CLN28HPC 28nm DDR 4/3 PHY - 3200Mbps

The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. ...

16
Gen2 DDR multiPHY - TSMC 28HPC

Support for JEDEC standard LPDDR2, LPDDR3, and DDR3 SDRAMs ; When combined with a DesignWare DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/LPDDR2/LPDDR3 ...

1 Testimonial
Sean Mitchell, Chief Operating Officer, Movidius

17
LPDDR4/3/2 DDR4/3/2 ComboPHY

The Mixed-Signal LPDDR4/3/2 DDR4/3/2 Combo PHYs with industry standard DFI V2.1 interface provide the most advanced physical interface solutions for ICs requiring access to all sorts of JEDEC ...

18
DDR Enhanced Memory Controller (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2

"The enhanced Universal DDR controller (uMCTL2) offers a single port Host Interface. the uMCTL2 is capable of controlling JEDEC standard DDR2, DDR3, Mobile DDR and/or LPDDR2 SDRAMs. The uPCTL ...

19
DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2

The DesignWare Basic Universal DDR controllers consist of the Universal DDR Protocol Controller (uPCTL) and the Universal DDR Memory Controller (uMCTL), which support the JEDEC DDR3, DDR2, Mobile ...

20
LPDDR4 Add-On for DDR Enhanced Universal Memory Controller (uMCTL2)

Synopsys offers several Universal DDR controllers, which use a DFI-compliant interface between the Memory or Protocol Controller IP and PHY. The DesignWare Universal DDR controller family consists ...

21
TSMC CLN28HPC 28nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

22
TSMC CLN28HPC 28nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

23
TSMC CLN28HPC 28nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

24
High Efficiency FPGA Memory Controller (DDR3, DDR4, ...)

The DDR/DDR2/DDR3-SDRAM memory controller IP Core supports both Single Data Rate (SDR) and Double Data Rate (DDR / DDR2 / DDR3) SDRAM devices. The memory controller IP Core is an assembly ...

25
ONFI 3.2 NV-DDR2 PHY in GDSII

The ONFI 3.0 NV-DDR2 PHY, compliant to ONFI 3.0 electrical interface, delivered in hard macro, is process technology proven and easy to integrate. This ONFI 3.0 PHY, supporting NV-DDR2 up to ...

26
Memory controller (SDRAM or DDR SDRAM)

The logiMEM SDR/DDR SDRAM controller provides a powerful, yet simple-to-use interface between the industry standard memory devices and several processor or DMA devices which share the same physical ...

27
Memory controller (SDRAM or DDR SDRAM) and Arbiter

The logiMEM_arb Memory Controller and Arbiter IP core, from Xylon logicBRICKS IP library, allows users to easily connect different SDRAM memories to the FPGA chip. Designed specially for Xilinx ...

28
DO-254 DDR Memory Controller 1.00a

A dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the most popular memory standards. Note: Spartan-6 equivalent of ...

29
7 way DDR combo

The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and the DDR voltage reference cell providing both ...

30
DDR SDRAM Controller

Supports industry standard Double Data Rate (DDR) SDRAM. ; Designed for ASIC and FPGA implementations in various system environments. ; Programmable memory size and data width. ; Supports industrial ...

31
DDR2 SDRAM Controller

Supports industrial standard Double Data Rate (DDR) and Double Date Rate2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes. ; Page hit detection to support multiple column accesses within the ...

32
Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core

MemConnect™ is a Comprehensive, Customizable, and Silicon Proven IP Solution for memory system design. It is a complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile ...

Access MemConnect Online

33
100~450MHz DDR DLL with 80 Phase Selection, SMIC0.1.3um

The AR531S13 is a low-jitter low power dual channel delay locked loop (DLL) design support for DDR application. It is featured with a wide output frequency range from 100MHz to 450MHz. The system ...

34
GF L65G 65nm DDR DLL - 93MHz-465MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

35
GF L65LP 65nm DDR DLL - 104MHz-520MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

36
TSMC CL018LV 180nm DDR DLL - 101MHz-505MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

37
UMC L130LL 130nm DDR DLL - 78MHz-390MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

38
UMC L40G 40nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

39
GF L28HPP 28nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay ...

40

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