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New Silicon IP
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Aeonic Generate™ AWM3 [PLL] actively responds to droop and enables DVFS with advanced clock health and droop telemetry
- Droop and DFS/DVFS response profile
- Programmable droop and DFS/DVFS response rate
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3.3V general purpose I/O for 28nm CMOS
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
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OTP One Time Programmable IP Samsung 90CIS
- Small IP Size
- High reliability
- Radiation hardening
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112Gbps VSR to extended LR SerDes IP on TSMC N7/N6
- Excellent performance for VSR to extended LR channels from 1G NRZ to 100Gbps PAM4 data rates
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112G Ultra-Low Power VSR PHY in TSMC N5 for optical modules and accelerators
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA ...
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Fast Fourier Transform IP Core
- Supports forward and inverse complex FFT
- Supports transform length (N) from 23 to 2¹⁶
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NPU
- 20% more energy efficient than Ethos-U55 and Ethos-U65, enabling future use cases in a sustainable way.
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64-bit, highly efficient application RISC-V CPU
- GPU integration
- Security at the forefront
- Ecosystem ready
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Crypto Module IP core
- Compatible with applicable NIST, IETF, and IEEE standards, RFCs, and test vectors for compliance and certification programs
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Multi-protocol wireless plaform integrating 802.11ax (Wi-Fi 6), Bluetooth 5.4 Dual Mode, 802.15.4 (for Thread, Zigbee and Matter)
- Turnkey integrated multi-protocol hardware and software platform
- Faster TTF (Time to Fab) and TTM (Time to Market)
- Integrated unified testbench
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PCIe 6.0 PHY for TSMC N6
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
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10Base-T/100Base-TX Fast Ethernet PHY
- Comply with IEEE 802.3u and IEEE 802.3 standard
- Support IEEE 802.3az 2010 Energy Efficient Ethernet
Top Silicon IP
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1
Secure Boot Hardware Engine
- Ensures integrity and authenticity of boot image
- Prevents any firmware down-grade (anti-rollback)
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2
AI Processor Accelerator
- OPTIMIZED COMPUTATION - >80% Utilization
- LOW MEMORY - 16X Reduced
- SPEED - 10-30x Lower Clock Cycles
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3
RISC-V GPGPU for 3D graphics and AI at the edge
- Unparalleled RISC-V flexibility & programmability
- Compelling ultra-low power 3D for wearables & aiot
- Enabling your ai application without additional silicon cost
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4
NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
- Support wide range of activations & weights data types, from 32-bit Floating Point down to 2-bit Binary Neural Networks (BNN)
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5
Upgraded PUF-based Crypto Coprocessor (Compliant with TLS 1.3 / FIPS 186-5)
- PUF-based Hardware Root of Trust (Riscure Common Criteria Certified)
- Comprehensive Crypto Engine (NIST CAVP Certified)
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MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
- Supports M-PHY HS-G4 and is available in TSMC 40G and other nodes
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7
12-bit, 8-GSPS DAC Ultra Low Power on 7nm
- 7nm FinFet
- 12-bit resolution
- 8-GSPS update rate
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8
PCIe 5.0 PHY for SF5
- Physical Coding Sublayer (PCS) block with PIPE interface
- Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
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9
AES IP Core
- supports encryption and decryption
- supports 128, 192, and 256-bit key lengths
- has masked and non-masked modes
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Gigabit Ethernet PHY
- Comply with IEEE 802.3ab, 802.3u, and 802.3
- Support IEEE 802.3az Energy Efficient Ethernet
- Support IEEE 802.3u Auto-Negotiation and Parallel Detection
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General Purpose Neural Processing Unit (NPU)
- Hybrid Von Neuman + 2D SIMD matrix architecture
- 64b Instruction word, single instruction issue per clock
- 7-stage, in-order pipeline
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12
Low Dropout (LDO) Capless Regulator, 25mA output, GF 22FDX
- Input voltage of 1.2V
- Output voltage of 0.79V to 0.86V
- Up to 25mA output current.
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