ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
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Digital Core Design in cooperation with DCD-SEMI Unveils DCAN-XL: Revolutionary CAN XL IP ...
Designed to bridge the gap between CAN FD and 100Mbit Ethernet, the DCAN-XL sets a new standard in high-speed, reliable data transmission for automotive ... Read
Andes, HiRain, and HPMicro jointly announced that the three parties will cooperate to combine the AndesCoreTM RISC-V processor series, the HPMicro HPM6200 ... Read
M31 Technology announced at today’s earnings conference call (05/09) that the consolidated revenue for the first quarter of 2024 was NT$342 million, ... Read
Partner Highlight
Under a contract with the European Space Agency (ESA), Frontgrade Gaisler is designing a new RISC-V processor tailored to meet the requirements of microcontrollers ... Read
X-Silicon Announces a NEW Low-Power Open-Standard Vulkan-Enabled C-GPU™ - a RISC-V Vector ...
The Open-Standard C-GPU solutions, offered as IP blocks and software, enable leading processor companies to develop low-power SoCs for Next Generation ... Read
VESA Elevates PC and Laptop HDR Display Performance with Updated DisplayHDR Specification
VESA today announced that it has published a major update to its widely adopted High-Performance Monitor and Display Compliance Test Specification (DisplayHDR), ... Read
Industry Expert Blogs
Fabio Malatesta, Frontgrade Gaisler
Synopsys
By Deep Mehta, Cadence
By Hezi Saar, Synopsys
Industry Articles
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The Rise of RISC-V and ISO 26262 Compliance
Simon Wang
Andes Technology -
Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)
Lakshmi Jain
Synopsys -
SoC NoCs: Homegrown or Commercial Off-the-Shelf?
Andy Nightingale
Arteris -
From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Vincenzo Liguori
Ocean Logic -
Embracing a More Secure Era with TLS 1.3
Lawrence Liu
PUFsecurity -
New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
Anton Shilov
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Maximizing ESD protection for automotive Ethernet applications
Andreas Hardock
Nexperia -
The role of cache in AI processor design
Frank Schirrmeister
Arteris