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Oct. 30, 2015 -
Can agile methodologies typically used in software development bring more efficiency to chip design? For UC Berkeley Professor Borivoje Nikolic, the answer is, why not? “Twenty years ago, technology people had fun making fun of ITRS predictions,” said Nikolic during his Tuesday morning keynote talk ...
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Jan. 13, 2011 -
A majority (if not all) SoCs today are mixed signal. Increasingly, the analog and digital portions of the design are inseparable. It is not possible any more to decompose them into separate analog and digital functions. Nothing can be treated as a black box and handed off to the other side. The new ...
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Jun. 07, 2018 -
Debugging the complex serial protocols is the biggest challenge verification engineers face. It’s one of the most time and effort consuming activity affecting the schedule of every project. Traditional debug methodologies use a combination of loosely connected waveforms, log files, messages, and documentation, ...
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Jun. 06, 2018 -
Debugging the complex serial protocols is the biggest challenge verification engineers face. It’s one of the most time and effort consuming activity affecting the schedule of every project. Traditional debug methodologies use a combination of loosely connected waveforms, log files, messages, and documentation, ...
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Mar. 20, 2017 -
The SoC industry depends upon the availability of validated IP. SoC designs require a huge investment, and assume the external IP that is licensed from outside parties satisfies all functional and electrical specifications. To support that requirement, IP providers typically pursue a strategy to demonstrate ...
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Jun. 26, 2016 -
Background This project involved DFT implementation and execution of a complex Consumer SoC. T&VS’ expertise in development of DFT methodologies for complex designs and track record of providing a wide range of DFT services from scan insertion to JTAG meant that the customer could rely on T&VS to ...
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Apr. 25, 2016 -
Samsung Foundry had an intimate gathering recently for 200 customers and partners that I missed, but I know several people who attended. This event was a precursor to #53DAC where Samsung has the largest foundry presence. I was able to clarify what I had heard via a phone call with Kelvin Low so here ...
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Sep. 18, 2015 -
Greater productivity, lower power, smaller die size and greater bandwidth await teams that adopt proven methodologies to streamline design in mature geometries. Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here’s why: There ...
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Sep. 18, 2015 -
NVM Express or the Non-Volatile Memory Host Controller Interface (its prior name was NVMHCI, now shortened to NVMe) is a host-based software interface designed to communicate with Solid State storage devices across a PCIe fabric. The current Synopsys NVMe Verification IP (VIP) is a comprehensive testing ...
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Apr. 13, 2015 -
UVM verification methodology & System Verilog have become the de-facto standard for IP level functional verification. At Arrow Devices we have created multiple complete and customizable verification solutions successfully using UVM Verification methodology and SystemVerilog. During this process of VIP ...
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Mar. 09, 2015 -
After years of innovation in verification of increasingly complex should we now turn our attention to the design process itself? Since starting in verification in the early 90’s I have witnessed the introduction of code and functional coverage, constrained random, assertions, numerous metrics, formal ...
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Mar. 06, 2015 -
Technical press coverage traditionally focuses on the bleeding-edge nodes because that’s where the biggest challenges are. But today, our industry sits astride two distinct paths: One, next-generation process nodes. But the second path is mature nodes, which are getting extended life thanks to exploding ...
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Jan. 08, 2015 -
Let's look at a variety of "Design for Verification" techniques aimed at reducing bugs and making designs easier to verify. After years of innovation in verification of increasingly complex designs, should we now turn our attention to the design process itself? Since starting in verification in ...
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Aug. 29, 2014 -
As the 3-D memory market matures, it continues to incubate new application opportunities and confront new challenges. Some of the challenges faced by 3D memory adoption range from technology to cost and design. On the technology front, many of the initial challenges around the interconnect reliability ...
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Jul. 28, 2014 -
As Moore's Law reverses and 20, 16, and 14 nanometer processes become more expensive, SoC cost reductions must come from design innovations within more mature processes and established methodologies. The days are over when companies can expect to make a profit by introducing a so-so product at first ...
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Jun. 09, 2014 -
SAN FRANCISCO--Sluggish growth in the EDA industry, which has frustrated vendors for a decade, can be reversed by tapping into new budgets and application areas. That was the message from Wally Rhines, Mentor Graphics CEO, during a presentation here at the 51st Design Automation Conference. Rhines, ...
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May. 28, 2014 -
IP integration is central to Sonics’ on-chip network business and technology strategies. We founded our company in 1996 based on the promise of IP integration to address the increasing silicon real estate afforded by Moore’s Law. Our company name, Sonics, is an acronym for Systems On ICs. For nearly ...
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Mar. 10, 2014 -
Smartphones, cloud computing, and the Internet of Things will dramatically increase our quality of life, according to veteran EDA investor Jim Hogan (right). But speaking at a Cadence-sponsored lunch at DVCon on March 4, 2014, Hogan also noted that these new technologies are causing "abundant chaos" ...
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Mar. 03, 2014 -
BARCELONA, SPAIN—It's hard (and probably intellectually dishonest) to boil down a huge event like Mobile World Congress 2014 into a single theme, but I'll give it a shot. If you wanted to pull a single, glimmering thread through all the electronics innovation packed into the Fira Gran Via ...
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Jan. 28, 2014 -
It wasn't too long ago—perhaps even 5 to 10 years ago—that EDA and IP cores made strange bedfellows. If you've been in the industry for a few years, you remember those days (think "star IP" for one thing). Well, times change quickly in our industry. Today, IP cores are a fundamental part ...
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Nov. 28, 2013 -
Carey Robertson, Mentor Graphics EETimes (11/27/2013 01:48 PM EST) All of the major foundries have announced FinFET technologies for their most advanced processes. Intel introduced this transistor at the 22 nm node, TSMC for their 16 nm process, and Samsung and Globalfoundries are introducing it for ...
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Oct. 03, 2013 -
There are some inescapable truths in electronics design: The more challenges we overcome, the more we want to confront new ones and topple them. Today, we know, the level of complexity for most designs is staggering. To achieve our cost and form factor design goals, we are deep into the era of mixed-signal ...
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Aug. 06, 2013 -
Many products and methodologies are available for block-level verification, but system-on-chip (SoC) interconnect analysis is not so well served. At a recorded Cadence Theater presentation at the 2013 Design Automation Conference, Ravi Kalyanaraman, Verification Manager at Marvell Technology ...
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Jul. 03, 2013 -
In this blog, we are going to explore an alternative to the traditional FPGA approach to creating a custom system. Configurable processors can implement many compute oriented functions FPGAs can address but with some distinct advantages. I talked to Bob Beachler, vice president of marketing, operations, ...
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Jun. 12, 2013 -
Keynote speeches at electronic design conferences tend to focus on high-level industry issues. The "Designer Keynote," part of the Designer Track at the recent Design Automation Conference (DAC 2013), was different. In engineer-to-engineer talks, design managers from Qualcomm and Texas Instruments ...
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Mar. 06, 2013 -
While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts ...
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Dec. 17, 2012 -
Today, EDA requires specialization. Elaborating on EDA over the past decade, Dr. Walden (Wally) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA, said that PCB design has been flat despite growth in analysis, DFM and new emerging markets. Front end design ...
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Nov. 02, 2012 -
In this column, I'm starting a mini-series on the development of Intellectual Property (IP) cores from FPGA suppliers. The subject of IP cores from third-party vendors will be a follow-on topic since there are significant issues that differ between IP delivered from the FPGA manufacturers and third-party ...
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May. 03, 2012 -
At an EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given the right tools ...
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Mar. 08, 2012 -
Last week was DVCon, probably the best conference of the year for those interested in functional verification. DVCon stands for Design and Verification Conference and it used to be that it concentrated on design. That was when languages such as Verilog and VHDL were the hot issues of the day. Today, ...
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Dec. 07, 2011 -
At this point, everyone has reported on the merger of OSCI and Accellera, two standards groups that operate in the EDA and IP domain. The principle output from OSCI has been the SystemC language and technologies surrounding it, such as the TLM 2.0 transaction level modeling interface. Accellera has ...
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Nov. 18, 2011 -
One of the major advances in SoC design methodologies more than a decade ago was the decoupling of the network-on-chip (NoC) from the individual IP cores throughout the SoC. This was (and is) accomplished through the use of carefully specified sockets such as OCP, the old VSIA VCI and (somewhat later) ...
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Sep. 27, 2011 -
As Moore’s Law continues to drive the semiconductor industry to smaller and faster transistors, 40nm chips are state-of-the-art, 32nm/28nm cores are right around the corner, and companies are now planning their 20nm flows, methodologies, and products. Foundries have been working tirelessly over the ...
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Aug. 18, 2011 -
One of the great debates of the last ten years in the software world has been the question of Agile Development. Given the growing role of software in an SoC project, it seems fair to ask if Agile techniques could-or should-be applied to the enormous OS porting, driver development, middleware integration, ...
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Apr. 21, 2011 -
Developing memory IP isn't easy - it's repetitive full-custom work that requires verification of many possible configurations. While full automation isn't possible, there are ways in which design tools and methodologies can make the task much easier. A recent conversation with engineers at Kilopass ...
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Apr. 11, 2011 -
System-on-chip (SoC) design teams have learned they can be much more productive by acquiring processor and interface IP. But most teams still build their own memory and storage controllers - a task that is becoming more difficult, and returning fewer benefits, as complexity grows. Memory and storage ...
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Feb. 07, 2011 -
There's been much talk about the tools and methodologies needed for next-generation electronic systems design, but not so much about the people behind them. The people side of system-level design became clearer at a DesignCon panel titled "Who is the Designer of the Future?" One conclusion: RTL designers ...
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Jan. 13, 2011 -
Two main languages, both IEEE standards, are in use today for constrained-random verification - SystemVerilog and the e language. Which is best, under what circumstances? Geoffrey Faurie, a member of the Functional Verification Group at STMicroelectronics, has some definite opinions about that question. ...
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Jan. 05, 2011 -
Device driver software is an essential part of any system-on-chip offering. But who develops and verifies this software, and what tools and methodologies do they use? This is an increasingly vexing question for many design teams - but it's absolutely critical as the industry moves towards application-driven ...
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Jan. 03, 2011 -
As outlined in a prior post, new advances in formal and multi-engine technology (like Incisive Enterprise Verifier or "IEV") enables users to do complete verification of design IP using only assertions (i.e. no testbench required!) -- especially for blocks of around 1 million flops or less. Given ...