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Friday, May 16, 2025

• Perforce Partners with Siemens for Software-Defined, AI-Powered, Silicon-Enabled Design
• Semidynamics: From RISC-V with AI to AI with RISC-V
• TSMC Board of Directors Meeting Resolutions
• Arm Evolves Compute Platform Naming for the AI Era

Thursday, May 15, 2025

• Secafy Licenses Menta's eFPGA IP to Power Chiplet-Based Secure Semiconductor Designs
• Arteris Announces Financial Results for the First Quarter and Estimated Second Quarter and Updated Full Year 2025 Guidance
• Perforce Partners with Siemens for Software-Defined, AI-Powered, Silicon-Enabled Design

Wednesday, May 14, 2025

• Siemens leverages AI to close industry's IC verification productivity gap in new Questa One smart verification solution
• Rambus Delivers Industry-Leading Client Chipsets for Next-Generation AI PC Memory Modules
• 5G-OT Alliance launched to bring 5G/LTE to OT environments
• Synopsys ramps up collaboration with Taiwan's TSMC on A16 process

Tuesday, May 13, 2025

• RISC-V International Promotes Andrea Gallo to CEO
• See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
• Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
• SMIC Q2 revenues to take 6% hit due to tool maintenance and validation issues
• Alps Alpine Adopts Silvaco's Jivaro Pro to Accelerate SPICE Post-Layout Simulation
• Arteris Q1 2025 presentation highlights 28% revenue growth, strategic automotive wins
• Historic Quantum Technology Agreement Signed by EU, Japan
• QuickLogic Reports Fiscal First Quarter 2025 Financial Results
• Renesas Partners with Indian Government to Drive Innovation Through Startups and Industry-Academia Collaboration, Strengthening India’s Semiconductor Ecosystem
• TSMC Board of Directors Meeting Resolutions

Monday, May 12, 2025

• Ceva, Inc. Announces First Quarter 2025 Financial Results
• Keysom Unveils Keysom Core Explorer V1.0
• Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
• RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
• Samsung's 12nm-class Automotive LPDDR5X: DRAM for safety-critical centralized automotive systems
• UK takeover panel gives Qualcomm till May 27 to make a bid for Alphawave

Friday, May 9, 2025

• SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
• Imagination Announces E-Series: A New Era of On-Device AI and Graphics
• VESA Releases Compliance Test Specification Model for DisplayPort Automotive Extensions Standard
• KEYSOM is heading to RISC-V Summit Europe in Paris!
• Meet DCD-SEMI at GITEX Europe 2025 — and RnD Con 2025!
• PQSecure Partners with Menta SAS to Demonstrate Leakage-Resistant PQC IPs on eFPGA Fabric

Thursday, May 8, 2025

• Kyocera Licenses Quadric's Chimera GPNPU AI Processor IP
• Xylon Introduces Xylon ISP Studio
• Xylon at ADAS&AVT Expo Europe 2025
• Cadence and AVCC to Advance Physical AI Innovations for Autonomous Vehicles
• Tensilica AI co-processor for automotive
• $50m quantum computing lab for Paris
• The future of AI runs on the GPU
• Cadence Accelerates Physical AI Applications with Tensilica NeuroEdge 130 AI Co-Processor
• Axiomise Featured Gold Sponsor at RISC-V Summit Europe Next Week in Paris

Wednesday, May 7, 2025

• Optimized SAR ADCs, Sigma-Delta ADCs, DACs, and Audio CODECs for IoT, MCU, SoC, and Consumer Applications
• EDA Companies Throw Support Behind TSMC's New A14 Process
• MIPI C-PHY v3.0 Adds New Encoding Option to Support Next Generation of Image Sensor Applications
• Keysight Expands USB Standards Support in System Designer for USB
• Cybord's Visual AI solution to be integrated with Siemens' Opcenter MES
• €15m for European image sensor breakthrough
• AI vs. AI: Both Friend and Foe in Cybersecurity
• Rapidus Starts Path to Advanced Chipmaking in Japan Government-backed startup's 2-nanometer pilot production gets underway
• Imec and TNO open Holst Centre Photonics Lab at High Tech Campus
• Numem Appoints Former Intel Executives to Leadership Team
• Agile Analog appoints CEO to drive growth

Tuesday, May 6, 2025

• CELUS Design Platform integrates with Cadence's OrCAD X Platform
• Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
• Enabled on makeChip and powered by Racyics, the SpiNNaker2 chip forms the core of the newly launched SpiNNcould supercomputer!
• Boss Semiconductor's CEO Park Jae-hong aims to disrupt Qualcomm's automotive chip dominance
• Synopsys slides into design enablement role in quantum computing
• AMD Reportedly Drops Samsung Foundry in Favor of TSMC's 4nm Production in Arizona
• Excelliance MOS Adopts Silvaco DTCO Flow for the Development of Next-Gen Silicon Carbide Devices
• Agile Analog appoints CEO to drive growth