Sep. 09, 2008 - With these enhancements, project managers can now more easily create verification plans, expand the scope and scalability of project metrics being managed, and uniquely combine formal verification, testbench simulation, and verification acceleration metrics for integrated verification process management. ...

Sep. 08, 2008 - In Breakthrough for System-Level Design, Cadence Reveals Technologies to Enable Early Exploration of Chip and System Power Requirements

Sep. 04, 2008 - Certitude is the first commercial functional qualification software product for companies developing systems on a chip (SoCs) or integrating intellectual property (IP) blocks. Certitude certifies that if a semiconductor chip design had a bug, it would be found.

Aug. 25, 2008 - Cosmic Circuits was looking for a SPICE simulator that would deliver a significant boost in speed without compromising on accuracy. The Spectre simulator, with its recently introduced turbo technology, enabled Cosmic Circuits to improve simulation runtime for design verification—accelerating time ...

Aug. 19, 2008 - Mentor Joins Altera’s DO-254 Global Partner Network; Announces Joint Development of DO-254-Certifiable IP

Aug. 19, 2008 - Imperas models of MIPS® processor cores will be verified by MIPS Technologies under the MIPS-Verified™ program.

Aug. 15, 2008 - Cadence Design Systems today announced that it has withdrawn its proposal to acquire all of the outstanding shares of Mentor Graphics common stock

Aug. 07, 2008 - BitSim as a QVP partners provides support for advanced verification methods, conversion services, training and consulting based on Mentor Graphics industry leading Questa verification platform.

Aug. 04, 2008 - Enables Design Reuse; Extends FPGA Core Operating Voltage Range; and Allows Users to Compare and Contrast Multiple Power Scenarios

Jul. 31, 2008 - The OVM, which Cadence Helped Develop, Enabled KPIT Cummins to Quickly Find Bugs in Its IP Design

Jul. 29, 2008 - OVM Enables OKI to Improve Verification IP Integration and Compress Testbench Development by 30%

Jul. 24, 2008 - Cadence Design Systems, Inc. today reported second quarter 2008 revenue of $329 million, compared to revenue of $391 million reported for the same period in 2007.

Jul. 21, 2008 - The goal of the project is to provide an integrated Globally Asynchronous, Locally Synchronous (GALS) design flow, together with novel Network-on-Chip (NoC) capabilities.

Jul. 17, 2008 - Mentor Graphics today announced that its virtual prototyping tool, SystemVision™, supports Design for Six Sigma (DFSS) methodologies to achieve cost-effective design innovation by a model-driven development process.

Jul. 14, 2008 - Cadence today introduced Cadence® C-to-Silicon Compiler, a high-level synthesis product that improves designer productivity up to 10 times in creating and re-using system-on-chip IP

Jul. 09, 2008 - Revenues increased by 43% to NT$4,469 million in the first half of 2008, compared to NT$3,133 million in the same period of 2007.

Jun. 24, 2008 - Veriest Verification and HDL Design House decided to collaborate closely on delivering design and verification services to the Israeli market.

Jun. 17, 2008 - The transaction price represents a total enterprise value of $1.6 billion on a fully diluted basis, which reflects Mentor Graphics' net debt of $69 million.

Jun. 16, 2008 - Customers Benefit From 2-5X Faster RF Analysis With Virtuoso Spectre Turbo Technology, and Fast and Accurate Electromagnetic Analysis Delivered by Virtuoso RF Designer

Jun. 12, 2008 - Tensilica has signed a partnership agreement with Imperas to allow fast functional, instruction accurate models of its popular Xtensa and Diamond Standard processors to run on Open Virtual Platform (OVP) based virtual platforms.

Jun. 09, 2008 - Cadence today announced the availability of the first two advanced testbench verification IP (VIP) products that are compliant with the Open Verification Methodology (OVM)

Jun. 09, 2008 - Reference Flow Uses CPF-Enabled Cadence Low-Power Solution and Key DFM Technologies for Advanced Node Designs

Jun. 09, 2008 - CPF-Based 65nm Low-Power Reference Design Flow Address Complex Design Issues and Accelerates High-Performance, Low-Power Designs

Jun. 09, 2008 - Power management capabilities enhanced with integration of Eclypse Low Power Solution

Jun. 09, 2008 - Comprehensive Flow Enhanced with Integration of Eclypse Low Power Solution Enabled by Unified Power Format

Jun. 06, 2008 - The Western Europe representative of HDL Design House IP products and design and verification services is EDA4YOU, Karlsruhe, Germany

Jun. 05, 2008 - Certess today announced that Toshiba Corporation, Japan's leading semiconductor manufacturer, adopted Certitude, the functional qualification tool, in their recent system-on-a-chip (SoC) for digital TV.

Jun. 03, 2008 - Standards-based Solutions for Pre-silicon Software Development Accelerate Collaborative Development of the Industry’s First Triple-Core Automotive MCU

Jun. 03, 2008 - Synopsys today announced that it has collaborated with ARM and Renesas Technology to define the industry's first methodology to address the rapidly increasing complexity of low power verification.

Jun. 03, 2008 - With its advanced tradeoff capabilities, SiWare Memory users can achieve static power savings of up to 35 percent, 70 percent or 90 percent depending on their selection of the built-in light sleep, deep sleep and shut-down modes available in 40nm memories.

Jun. 02, 2008 - Avery Design Systems today announced Insight, a new breed of formal analysis tool that delivers a deterministic bug hunting and coverage closure process with unprecedented flexibility and complements today’s SystemVerilog-based intelligent testbench methodologies.

May. 28, 2008 - CPF-Based Faraday SoCompiler Design Services Leverages the Cadence Low-Power Solution to Achieve> 99% Leakage Reduction and 65% Dynamic Power Reduction and Significantly Reduced Design Time

May. 22, 2008 - This latest package release provides a complete and an accurate solution for simulating memories, including support for most of the memory technologies, including DRAM, SRAM, Flash, and Card memories, and several standard protocols.

May. 21, 2008 - IPextreme and IP Square today announced that IP Square has licensed the ColdFire® Architecture for use across their product line.

May. 15, 2008 - Pantel International and IPextreme today jointly announced the establishment of a strategic development initiative addressing the problem of automatic location of 911 emergency calls within an Internet protocol (IP) telephone network built on a ColdFire® microprocessor platform.

May. 13, 2008 - Faraday Technology today announced that it has successfully integrated a hardened 533Mhz ARM(R) compliant core -- FA626 in a complex 130nm SoC ASIC for Radioframe Networks.

May. 13, 2008 - Cosmic Circuits Receives IBM Advanced Business Partner Certification and Completes 90nm Silicon Validations in the Power-Management and A/D Converter Space

May. 12, 2008 - Synopsys today announced that it is donating its complete implementation of the proven VMM verification methodology for SystemVerilog, including the VMM Standard Library and VMM Applications, to Accellera to enable verification interoperability standardization.

May. 12, 2008 - CoWare is offering its customers integration support for accelerated C models generated by Agility’s RMS and MCS products into the entire range of CoWare’s ESL 2.0 solutions.

May. 12, 2008 - VeriSilicon has joined the Power Forward Initiative (PFI) and plans to offer a Common Power Format (CPF)-based design solution for its ASIC customers.