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Verilog vhdl IP Listing

124 IP Cores (1 - 40)

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Magillem Registers System Integration Automation

Cost-effective and scalable, Magillem Registers offers a unified methodology for HW/SW Interface automation. The Registers approach targets the traditional need to manage registers efficiently ...

1
HW/SW interface foundation for design innovation

Check out our new product, Magillem Registers, making the most of Magillem 5 and CSRCompiler technologies to accelerate large and complex SoC designs through Hardware/Software Interface automation. ...

2
Video Tracking FPGA IP core for Xilinx and Altera

The T-COR-30 FPGA IP core implements the algorithm of automatic tracking of objects in video and calculation of their pa-rameters for solving guidance and target designation tasks. The IP core ...

3
Video Tracking FPGA IP core for Xilinx and Altera

The T-COR-31 FPGA IP core implements the algorithm of automatic tracking of objects in video and calculation of their pa-rameters for solving guidance and target designation tasks. The IP core ...

T-COR-31 Demo IP core for Xilinx 7-series FPGA

4
Video Tracking FPGA IP core for Xilinx and Altera

The FPGA IP core T-COR-32 implements the algorithm of automatic tracking of objects in video and calculation of their motion parameters. The core ensures a stable tracking of small-sized and ...

FPGA IP CORE VIDEO TRACKING (T-COR-32)

5
High Data Rate Demodulator

The High Data Rate Demodulator IP core can demodulate BPSK, QPSK, offset-QPSK (OQPSK), 8PSK and 16QAM modulation schemes, all to a high performance level and at high symbol rates. The demodulator ...

6
ISDB-T Modulator

The ISDB-T Modulator IP Core is a 3-layer ISDB-T hierarchical modulator compatible with the ARIB STD-B31 standard for Terrestrial Integrated Services Digital Broadcasting. The ISDB-T Modulator ...

7
High Data Rate Enhanced Demodulator

The High Data Rate Enhanced Demodulator IP Core can additionally demodulate 8QAM (3 shapes), 32/64QAM &16/32APSK, and contains an adaptive equaliser to reduce linear channel distortion such ...

8
High Data Rate Modulator

The High Data Rate Modulator IP Core efficiently realizes the digital baseband section of a high performance modem transmit path, including symbol mapping, matched filtering, sample interpolation, ...

9
ISDB-T Demodulator

The ISDB-T Demodulator IP Core is a 3-layer ISDB-T hierarchical demodulator compatible with the ARIB STD-B31 standard for Terrestrial Integrated Services Digital Broadcasting. The ISDB-T ...

10
16550D High Speed UART IP core - Universal Aysynchronous Receive/Transmit

Arasan 16550D High Speed UART IP core is a 16550-compliant Universal Asynchronous Receiver/Transmitter (UART) with FIFO or expanded FIFO. The UART performs serial to parallel conversion ...

11
LIN Bus Master/Slave Controller Core

Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication according to the LIN Protocol Specification. ...

12
Programmable Interrupt Controller

The Digital Blocks DB8259A Programmable Interrupt Controller core is a full function equivalent to the Intel 8259A and Harris / Intersil 82C59A devices. The DB8259A Interrupt Controller manages ...

13
Programmable Interrupt Controller (Synchronous)

The Digital Blocks DB8259S Programmable Interrupt Controller IP core is a full function equivalent to the Intel Intel 8259A / Intersil 82C59A / NEC uPD8259A devices, with the update to a synchronous ...

14
Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core

The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data blocks with 128-bit key (a 256-bit key version ...

15
USB 2.0 Host Controller (EHCI)

VHDL / Verilog source code provided ; USB EHCI specification compliant ; 33 MHZ PCI 2.1 compliant ; Supports low, full and high speed devices ; Technology independent ; Integrated root hub with ...

16
Embedded Host Controller 1. 1

VHDL / Verilog source code provided. ; USB1.1 specification compliant. ; Technology independent. ; Portable ‘C’ software stack provided. ; Integrated root hub with 1 to 3 ports. ; Supports ...

17
Embedded Host Controller 2.0

Portable ‘C’ software stack provided. ; VHDL / Verilog source code provided. ; USB2.0 specification compliant. ; Technology independent. ; Integrated root hub with 1 to 3 ports. ; Supports ...

18
USB2.0 On-The-Go

VinChip’s USB 2.0 High Speed OTG controller is designed for flexibility and ease of use and facilitates implementation of a wide variety of applications with fast turnaround time. This design ...

19
FFT/IFFT

The fast Fourier transform (FFT) MegaCore® function is a high-performance, highly parameterizable FFT processor. The FFT function implements a radix-2/4 decimation-in-frequency (DIF) FFT algorithm ...

20
FIR Compiler

The Altera® FIR Compiler II MegaCore function generates finite impulse response (FIR) filters customized for Altera devices. You can use the IP Toolbench interface to implement a variety of ...

21
Synthesizable 68000 Compatible CPU Core

The V68000 is a synthesizable VHDL (soft) core design which is object code compatible with Motorola's popular MC68000. The V68000 is intended to be used in system-on-a-chip applications constructed ...

22
PCI Compiler, 32-bit Master/Target

Altera's PCI Compiler provides a complete, easy-to-use solution for implementing a PCI interface with Altera devices. The PCI Compiler contains the Altera pci_mt32 and pci_t32 MegaCore functions ...

23
Reed-Solomon Compiler, Encoder

The Reed-Solomon (RS) compiler offers a fully parameterizable RS coder and RS decoder. RS coder/decoders (CODECs) are widely used for error detection and correction in a wide range of digital ...

24
Triple DES core

Implemented according to the X9.52 standard ; Implementation based on NIST certified DES core ; Also available in CBC, CFB and OFB modes. ; 112 or 168 bits keys supported. ; Both encryption ...

25
PCI Compiler, 64-bit Master/Target

Altera's PCI Compiler provides a complete, easy-to-use solution for implementing a PCI interface with Altera devices. The PCI Compiler contains the Altera pci_mt64, pci_t64, pci_mt32, and pci_t32 ...

26
Viterbi Compiler, High-Speed Parallel Decoder

The Altera® Viterbi Compiler generates high-performance, soft-decision Viterbi MegaCore® functions that implement a wide range of standard Viterbi decoders. Viterbi decoding (also known as ...

27
Viterbi Compiler, Low-Speed/Hybrid Serial Decoder

The Altera® Viterbi Compiler generates high-performance, soft-decision Viterbi MegaCore® functions that implement a wide range of standard Viterbi decoders. Viterbi decoding (also known as ...

28
AES core

Implemented according to the FIPS 197 documentation. ; Also available in CBC, CFB and OFB modes. ; Key size of 128, 192 and 256 bits. ; Both encryption and decryption supported. ; Fully synchronous ...

29
SHA-1 Processor

Suitable for data authentication applications. ; Fully synchronous design. ; Available as fully functional and synthesizable VHDL or Verilog soft-core. ; Xilinx and Altera netlist available ...

30
MD5 Processor

RFC 1321 compliant. ; Suitable for data authentication applications. ; Fully synchronous design. ; Available as fully functional and synthesizable VHDL or Verilog soft-core. ; Xilinx and Altera ...

31
I2C Master/Slave Interface

CoreI2C provides an APB-driven serial interface, supporting I2C, SMBus, and PMBus data transfers. Several Verilog/VHDL parameters are available to minimize FPGA fabric area for a given application. ...

32
QDRII SRAM Controller

The QDRII SRAM Controller MegaCore® function provides an easy-to-use interface to QDRII SRAM and QDRII+ SRAM modules. The QDRII SRAM controller ensures that the placement and timing are in ...

33
Core generator for finite impulse response filters

CoreFIR is a core generator for finite impulse response (FIR) filters. The core generator uses a distributed arithmetic implementation methodology to create FPGA-based digital filters. The ...

34
POS-PHY Level 4

The packet over SONET/SDH PHY (POS-PHY) Level 4 interface, first developed by the SATURN Development Group, was later adopted by the Optical Internetworking Forum (OIF) as the System Packet ...

35
Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core

MemConnect™ is a Comprehensive, Customizable, and Silicon Proven IP Solution for memory system design. It is a complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile ...

Access MemConnect Online

36
Embedded Tri-mode Ethernet MAC Wrapper

The CORE Generator™ Embedded Tri-mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper files for the embedded Tri-mode Ethernet MAC in Virtex™-4 FX ...

37
Baseline HDTV 1080p H.264/AVC Encoder Core

The OL_H264e core is a hardware implementation of the H.264 baseline video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the ...

38
Block Memory Generator

Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz The Block Memory Generator LogiCORE™ IP core automates ...

39
8051 Microcontroller

8031 software compatible microcontroller ; (includes serial & timers) ; Low cost - $495, Support available ; Small size ~300 Slices ; Use existing 8051 object code ; VHDL or Verilog support ...

40

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