D&R Videos

Demonstration of a CXL Interconnect on a FPGA-based ... from PLDA Jul 08, 2021 6:03	Thalia's AMALIA Design Enabler from Thalia Design Automation May 26, 2021 2:28	Ultra-Low Latency TSN Networks from CAST May 12, 2021 51:06
What are Codasip's application cores? from Codasip Feb 01, 2021 7:22	A Day in the Life of Gen-Z Vlog - IntelliProp from IntelliProp Sep 30, 2020 8:03	How DSP is Killing the Analog in SerDes from Alphawave IP, Inc. Sep 30, 2020 36:11
What is Processor Performance? from Codasip Sep 08, 2020 8:28	Expanding RISC-V processor portfolio from Codasip Sep 08, 2020 6:33	The Path to 200Gbps Serial Links from Alphawave IP, Inc. Sep 03, 2020 29:49
Thalia DA IP Reuse & Technology Analysis from Thalia Design Automation Jul 16, 2020 18:51	Using a patent portfolio to support a global semiconductor ... from SoundHound Inc. May 13, 2020 20:21	The Next Generation RISC-V Processors AndesCore™ ... from Andes Technology Corp. May 11, 2020 26:45
Learn how to configure a PCIe IP with an AXI interconnect ... from PLDA Jan 28, 2020 4:44	Status Update of RISC-V P Extension Task Group from Andes Technology Corp. Jan 16, 2020 7:30	Discover how to configure XpressRICH IP from PLDA Nov 25, 2019 5:09
Powering RISC-V SoC With 1 To 1000s Cores from Andes Technology Corp. Nov 07, 2019 27:28	Cadence PCIe 4.0 Receiver JTOL Test from Cadence Oct 17, 2019 1:43	Verification with Emerging Memory Models from Cadence Oct 17, 2019 4:12

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