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Collaboration on AI-Driven Design Flows for Optimization and Productivity, Advancements in Photonic IC Integration, Plus Broad IP Development on TSMC ... Read
TSMC Celebrates 30th North America Technology Symposium with Innovations Powering AI with ...
TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with ... Read
Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes ...
Today at the TSMC 2024 North America Technology Symposium, Siemens Digital Industries Software announced that ongoing collaboration with longtime partner ... Read
Partner Highlight
While sureCore focuses on cryogenic semiconductor design, Quantum Computing works on photonics-based technologies. Read
Credo Technology is set to showcase its latest SerDes IP and Chiplet technology at three upcoming Taiwan Semiconductor Manufacturing Company (TSMC) Symposium ... Read
As the latest addition to the Rambus portfolio of industry-leading interface and security digital IP for AI 2.0, the GDDR7 memory controller will provide ... Read
Industry Expert Blogs
Synopsys Blog Synopsys Editorial Team
Renesas Blog Daryl Khoo, Renesas
Codasip Blog David Higham, Codasip
Packetcraft Blog Laura Moore
New Products
GDDR7 Memory Controller
MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
UHF RFID EPC Gen2V2 physical interface on SMIC EEPROM CMOS 180 ...
32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 ...
High-performance mixed-precision NPU IP
ASIL B Ready PCIe 5.0 Integrity and Data Encryption (IDE) Security ...
DVB-S2X Wideband LDPC BCH Decoder
Aeonic Generate™ AWM3
3.3V general purpose I/O for 28nm CMOS
One Time Programmable IP on Samsung 90CIS
112Gbps VSR to extended LR SerDes IP on TSMC N7/N6
Fast Fourier Transform IP Core
ETHOS-U85 NPU
APXM-6200 - 64-bit, highly efficient application RISC-V CPU
SPMI Verification IP
BoW Verification IP
Simulation VIP for MIPI SoundWire-I3S
MIPI A-PHY Verification IP
UCIe Verification IP
Synthesizable DDR5 Bus Functional Model
SGPIO Verification IP-
Powerful vector DSP for 5G-Advanced Massive Compute - The Synopsys 1.6T Ethernet MAC IP is based on IEEE 802.3-2018 ...
- Secure-IC's Securyzr(TM) Network Security Crypto Accelerator ...
- Configurable controllers for PCIe 4.0 supporting Endpoint, Root ...
- 8-bit ≤25GSa/s High-speed Low power ADC in 16nm TSMC CMOS
Powerful vector DSP for 5G-Advanced Massive Compute- ARC NPX Neural Processing Unit (NPU) IP supports the latest, ...
- Broadcast quality video encoder for all NTSC and PAL video standards ...
- Scalable multicore architecture for a range of macrocells, small ...
- Automotive MIPI A-PHY Sink IP (2-Lane)
- Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 ...
Industry Articles
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From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Vincenzo Liguori
Ocean Logic -
Embracing a More Secure Era with TLS 1.3
Lawrence Liu
PUFsecurity -
New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
Anton Shilov
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Maximizing ESD protection for automotive Ethernet applications
Andreas Hardock
Nexperia -
The role of cache in AI processor design
Frank Schirrmeister
Arteris -
Time Sensitive Networking for Aerospace
CAST and Fraunhofer IPMS
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Understanding mmWave RADAR, its Principle & Applications
Snehal Buche
eInfochips -
Advanced Topics in FinFET Back-End Layout, Analog Techniques, and Design Tools
AsicNorth
