Lattice clock ip IP core / Semiconductor IP / Silicon IP

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Lattice Clock ip IP Listing

Configurable CAN Bus Controller IP with Flexible Data-Rate

I2C Bus Master / Slave Controller Interface with FIFO

I2C Master / Slave Controller with FIFO (AXI & AXI-Lite Bus)

Scalable UHD JPEG 2000 Encoder - 8 up to 16 bits per Component Lossy or Numerically Lossless Image & Video Compression

SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)

I2C Bus Interface - Master with FIFO

Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support

IrDA Controller

UART Core with SDLC Function

SMBUS & PMBUS Master/Slave controller

Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s

DCD's Universal Timers System

Enhanced Multiprotocol Serial Communication Controller

Configurable CAN Bus Controller with Flexible Data-Rate

Crest Factor Reduction IP

Deinterlacer

Display Interface Multiplexer

Divider

JESD204B IP Core

JESD207 IP

LPDDR SDRAM Controller

Median Filter

Video Frame Buffer

JPEG dual channel encoder

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