RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
1609 Results (561 - 600) |
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Nimbic Secures $6.9M Series B Financing
Jun. 02, 2011 - Nimbic today announced that new investor Austral Capital, and existing investors Madrona Venture Group and WRF Capital, have collectively invested $6.9 million in venture funding. -
Nimbic Launches Scalable and Secure Cloud Computing Solution for Electronic Design Automation
May. 31, 2011 - Nimbic (formerly Physware) today announced the open beta launch of nCloud, the world’s first scalable and secure cloud computing platform for electronic design automation (EDA). Effective immediately, nWave, the leading 3D full-wave EM solver for signal and power integrity (formerly PhysWAVE), and ... -
Paradigm Works Announces that VerificationWorks is Now UVM 1.0 Compliant
May. 30, 2011 - Paradigm Works today announced that its VerificationWorks™ verification productivity software suite is UVM 1.0 compliant. -
TSMC Completes 28nm Design Infrastructure, Design Partners Show Solutions at DAC
May. 26, 2011 - TSMC announced today that 28nm support within the Open Innovation Platform™ (OIP) design infrastructure is fully delivered, as demonstrated by 89 new 28nm designs scheduled to tapeout. -
Vennsa Unveils OnPoint with Powerful Triage Engine, Enhanced Accuracy, Increased Capacity
May. 18, 2011 - Vennsa today announced immediate availability of OnPoint™ with Triage, along with a set of performance-driven features to enhance accuracy and increase capacity. -
Atrenta Ships the Industry's Most Comprehensive RTL Platform
May. 17, 2011 - Atrenta has announced the availability of the next-generation release of its popular SpyGlass® product family. Atrenta has enhanced the SpyGlass family in multiple areas, including usability, debug, advanced linting, power estimation and reduction, CDC verification, constraints management, and testability. ... -
SpringSoft Rolls Out Advanced Technology Platform for Certitude Functional Qualification System
May. 11, 2011 - SpringSoft today announced advancements to its Certitude™ Functional Qualification System that enable broader and more efficient deployment of verification qualification methodologies. -
Cadence and TSMC Collaborate to Deliver DFM Services for TSMC Advanced Processes
May. 09, 2011 - Cadence today announced it has collaborated with TSMC to deliver their customers DFM expertise and technology in a service model. -
Cadence Announces Breakthrough in System Development to Meet Demands of "App-driven" Electronics
May. 04, 2011 - Cadence today announced a breakthrough in electronic design with a new suite of products that promises to cut system integration time by up to half for next-generation designs. Bringing hardware and software development closer together than ever before, the suite features four connected platforms that ... -
PLDA and Aldec Announce PCI Express DMA IP Supporting Advanced Verification Tools for FPGA Development
Apr. 28, 2011 - PLDA and Aldec today announced the immediate availability of PLDA’s EZDMA IP solution, supporting Aldec’s Riviera-PRO for Linux and Active-HDL for Windows. -
Cadence Reports Q1 2011 Financial Results
Apr. 28, 2011 - Cadence Design Systems today announced results for the first quarter of fiscal year 2011. Cadence reported first quarter 2011 revenue of $266 million, compared to revenue of $222 million reported for the same period in 2010. -
HDL Design House Joins the Cadence IP Alliance Program
Apr. 27, 2011 - HDL Design House today announced that it has signed a strategic agreement with Cadence Design Systems to join the Cadence IP Alliance program. -
Xylon Releases Complete Development Platform and Toolset for Multi-Camera Surround View Systems
Apr. 14, 2011 - Xylon today announced that it has released the logiVIEW-SVK, a complete development platform and toolset for developers of automotive multi-camera Surround View Driver Assistance (DA) Systems. -
Cadence Announces Availability of World's First DDR4 IP Solution
Apr. 11, 2011 - Cadencetoday announced a DDR4 solution. The solution includes hard and soft PHY IP; controller IP; memory models; verification IP; tools and methodologies; and signal integrity reference designs for the package and board. -
ChipStart Selects S2C to Facilitate Prototyping ChipStart's SoC System Management Options
Mar. 31, 2011 - ChipStart LLC announced today it has selected S2C, Inc. as a target vendor for prototyping and low volume deployment of ChipStart’s SSM SoC System Manager. -
Evatronix to Discuss Multi-configuration Challenges in IP Design at the D&R IP-SoC Day in Tel-Aviv
Mar. 30, 2011 - Evatronix announced today the presentation on multi-configuration challenges in IP design and delivery that will be held on April 6th during the Design&Reuse IP-SoC Day event in Tel-Aviv, Israel. -
Cadence Releases Industry's First Wide I/O Memory Controller IP Solution
Mar. 28, 2011 - Cadence Design Systems today announced that it is first to market with a licensable, wide I/O memory controller core, along with an integration environment, that brings PC-like performance to mobile applications like smartphones and tablets. -
Xilinx Ships World's First 28nm FPGA Device and Demonstrates Application Development Platform for Next Generation Systems
Mar. 21, 2011 - Xilinx today announced the beginning of the 7 series FPGA rollout with shipment of the first Kintex(TM)-7 K325T Field Programmable Gate Array (FPGA), marking the industry's fastest product rollout of next generation programmable logic devices built with 28nm technology. -
DOLPHIN Integration complete their offering with high added value trainings
Mar. 18, 2011 - Dolphin Integration have developed techniques based on behavioral modeling to speed-up simulation and on detectors to reduce verification time and increase hierarchical verification coverage. Now that these methodologies have proven their added-value, Dolphin is spreading these techniques externally ... -
OSCI Welcomes Adoption of SystemC AMS 1.0 Standard Inside Industrial Design Flows for Mixed-Signal System Design
Mar. 15, 2011 - OSCI announce the continuing industry adoption of the SystemC Analog/Mixed-Signal (AMS) 1.0 Standard for mixed-signal system-level design. NXP Semiconductors, STMicroelectronics and Infineon Technologies, are integrating SystemC AMS extensions into their respective ESL design methodologies and mixed-signal ... -
Cadence Enhances Unified Custom/Analog Flow to Boost Productivity at Nodes Down to 20nm
Mar. 14, 2011 - Cadence today announced major enhancements to its Virtuoso®-based custom/analog flow, boosting productivity across the entire flow from initial design specification to final GDSII and for process nodes down to 20 nanometers. -
Synopsys Announces FPGA Synthesis Support for Xilinx's Newest ISE Design Suite 13
Mar. 09, 2011 - Synopsys today announced Synplify Pro, Synplify Premier and Synphony synthesis support for Xilinx's latest ISE® Design Suite (IDS) 13, which provides support for their 28-nanometer (nm) 7 series FPGAs. -
ISE Design Suite 13 Kicks-off Broad Support for 7 Series FPGAs and Delivers Enhanced System Level Productivity With New Team Design Flow
Mar. 08, 2011 - Xilinx today announced the immediate availability of ISE(R) Design Suite ISE13. New to the award winning design tool and IP suite are enhancements which improve productivity across SoC design teams and progression towards true plug-and-play IP that targets Spartan(R)-6, Virtex(R)-6 and 7 series FPGAs, ... -
Mentor Graphics Transforms SoC Integration and Functional Verification with Next Generation Questa Platform
Mar. 01, 2011 - Mentor Graphics today announced that it has embarked on a corporate-wide strategy aimed at transforming the integration and functional verification of complex System on Chip (SoC) designs. The strategy targets both near-term and long-range challenges with a blend of tools and methodologies that span ... -
Cadence Opens and Extends Verification IP Catalog for Use Across Silicon, SoC and System Development
Feb. 28, 2011 - Cadence today detailed the extensive expansion of its broad portfolio of verification IP (VIP) and memory models. The Cadence® VIP offering boasts support of new protocols such as ARM® AMBA® 4 and MIPI to address early IP verification and integration through to system validation in demonstration ... -
Accellera Approves Universal Verification Methodology (UVM) Standard
Feb. 21, 2011 - Accellera approved version 1.0 of its Universal Verification Methodology (UVM) standard. -
Broadcom Expands Use of Cadence Verification Computing Platform to Tackle System Realization
Feb. 22, 2011 - Cadence today announced that Broadcom is expanding its use of the Cadence® Verification Computing Platform, Palladium® XP, to help validate its complex system designs before committing them to silicon. -
Achronix and Mentor Graphics provide state of the art physical synthesis support for Speedster22i FPGAs - the world's most advanced FPGAs leveraging Intel's 22nm process technology
Feb. 21, 2011 - Achronix today announced the closing of a formal agreement with Mentor Graphics to provide advanced synthesis support for Achronix Semiconductor’s Speedster22i Field Programmable Gate Arrays (FPGAs). -
MIT, TI tip 28-nm processor
Feb. 21, 2011 - At the 2011 International Solid-State Circuits Conference (ISSCC) here, Texas Instruments Inc. and the Massachusetts Institute of Technology (MIT) will outline what could be a major breakthrough in the gap between performance demands and battery capacity in the mobile space. -
Synopsys Invites Cadence Incisive and Mentor Graphics Questa Users to the Verification FastForward Program
Feb. 03, 2011 - Synopsys today announced the verification FastForward migration program. The program helps Cadence® Incisive® and Mentor Graphics® Questa® users to migrate to the VCS® functional verification solution and benefit from its superior technologies. -
Cadence Reports Fourth Quarter and Fiscal Year 2010 Financial Results
Feb. 03, 2011 - Cadence today announced results for the fourth quarter and fiscal year 2010. Cadence reported fourth quarter 2010 revenue of $249 million, compared to revenue of $220 million reported for the same period in 2009. -
Cadence Drives Giga-gate/Gigahertz Design at 28nm with New Digital End-to-end Flow
Jan. 31, 2011 - Cadence today advanced the design of giga-gate/gigahertz system on chips (SoCs) with a proven digital end-to-end flow at 28 nanometers that yields both performance and time-to-market advantages. -
Xilinx Acquires AutoESL to Enable Designer Productivity and Innovation With FPGAs and Extensible Processing Platform
Jan. 31, 2011 - Xilinx today announced the acquisition of high level synthesis leader AutoESL Design Technologies, Inc. -
ParadigmWorks Releases VerificationWorks for UVM, Enabling Faster Verification Project Rampup
Jan. 31, 2011 - Paradigm Works today announced that it has released VerificationWorks™, a verification productivity software suite that enables rapid project rampup for UVM, VMM, and OVM-compliant environments. -
Accellera Approves New Version of Electronic Design System Modeling Standard
Jan. 28, 2011 - Accellera announced today that its Board of Directors approved a new version of Accellera's Standard Co-Emulation Modeling Interface (SCE-MI) specification as a new Accellera verification standard. -
Avery Design Systems Synthesizes Microarchitecture-Level Assertions and Coverage Properties
Jan. 24, 2011 - Avery Design Systems today announced it has developed a new capability for Insight formal analysis tool which automatically synthesizes assertions and coverage properties and automates assertion and coverage based verification methodologies. -
Mentor Graphics Completes Test Chip with IC Implementation Flow for Common Platform 32/28nm Technology
Jan. 18, 2011 - Mentor Graphics today announced it has collaborated with the Common Platform Alliance (CPA) members, IBM, GLOBALFOUNDRIES and Samsung, to design a test chip using its netlist-to-GDSII solution for CPA 32nm and 28nm high-k metal gate (HKMG) IC manufacturing technologies. -
Cadence Introduces 32/28-Nanometer Low-Power RTL-to-GDSII Silicon Realization Reference Flow for Common Platform Alliance
Jan. 18, 2011 - Cadence today introduced a qualified 32/28-nanometer reference flow targeting Common Platform™ technology. Cadence® collaborated closely with members of the Common Platform alliance—IBM, GLOBALFOUNDRIES, and Samsung Electronics—to develop a flow from RTL synthesis to GDSII signoff for the advanced ... -
Synopsys Announces Production-Ready Lynx Design System Optimized for Common Platform 28-nm High-K Metal Gate Technology
Jan. 17, 2011 - Synopsys today announced it is delivering a low power, high-performance system-on-chip (SoC) design solution optimized for the Common Platform alliance (CPA) 28-nanometer(nm) high-k metal gate (HKMG) technology. -
GLOBALFOUNDRIES Unveils Industry's First 28nm Signoff-Ready Digital Design Flows
Jan. 13, 2011 - GLOBALFOUNDRIES today introduced the industry's first 28nm silicon-validated signoff-ready digital design flows to help chip designers deliver the next generation of power-sensitive mobile and consumer electronic devices.