How to Design Cost–Optimized Embedded System with ARM926EJTM Embedded System designers now have an alternative for developing optimized and affordable systems that are customizable in both hardware and software. eASIC’s Nextreme Structured ASICs provide you with the benefits of zero mask-charges, no minimum order, and 3-4 weeks turnaround. Our IP portfolio, including 150MHz soft ARM926EJTM processor, can help you build low-cost customized embedded system. Download White Paper by ARM and eASIC

Design Platform / Structured ASIC Articles

• How to achieve design flexibility for free using Structured ASIC approaches (Mar. 27, 2008)
  Under certain circumstances, it is possible over the lifetime of a design to reduce the time to market and/or production time without incurring additional costs.
  
  
• Viewpoint: Embrace platform-based design (Nov. 29, 2007)
  A fickle market and unpredictable consumer tastes make platform-based design a time- and money-saver for manufacturers.
  
  
• Using customizable MCUs to bridge the gap between dedicated SoC ASSPs, ASICs and FPGAs: Part 1 (Jun. 14, 2007)
  Custom ASICs always offer the best performance, power consumption, security and unit cost of any silicon-based solution. Cell-based ASICs provide the best characteristics because the poly and diffusion layers for interconnect, and transistors can be sized to optimize speed, density, and power dissipation according to each particular cell's requirements.
  
  
• Nextreme Structured ASICs: An alternative for designing cost-optimized ARM926EJ processor-based embedded systems (Mar. 19, 2007)
  Traditional IC design options that embedded system designers have had to choose from include fixed hardware devices such as standalone microprocessors, microcontrollers and ASSPs or configurable hardware devices such as FPGAs and cell-based ASICs. In this paper we present a new design option called Nextreme Structured ASICs which provide embedded system designers with a compelling alternative to custom embedded system design.
  
  
• ''Do's and Don'ts" when considering an FPGA to structured ASIC design methodology (Aug. 28, 2006)
  FPGA prototyping is more successful for structured ASICs compared to standard cell ASICs when the structured ASIC mirrors the resources available on the FPGA
  
  
• How to implement a digital oscilloscope in Structured ASIC fabric (Jul. 13, 2006)
  Structured ASICs provide quicker time-to-market and lower development costs than standard ASICs, while also providing higher performance and lower unit costs than FPGAs.
  
  
• Configurable SoCs speed turnaround (Jul. 06, 2006)
  Regardless of the fabric used, designers should be aware of a few do's and don'ts when designing configurable sections within an SoC.
  
  
• FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM (Jun. 08, 2006)
  This paper discusses a FPGA to structured ASIC conversion methodology that will reduce cost, risk, TTM and power consumption while maintaining or increasing performance.
  
  
• How hybrid Structured ASICs provide low cost solutions for mid-range applications (May. 10, 2006)
  Hybrid structured ASICs take the structured idea one step further, because the upper metal layers don't require the same level of precision as the base layers
  
  
• FPGAs and Structured ASICs: Low-Risk SoC for the Masses (Jan. 19, 2006)
  This paper will explain how new ASSP ventures face challenges that can derail success of a product even before the first device is sold, including market entry barriers such as time to market pressures, limited human and financial resources, and increased
  
  
• Routing density analysis of ASICs, Structured ASICs, and FPGAs (Oct. 19, 2005)
  This article uses well-known routing estimation techniques to analyze the trends of routing area requirements for standard cell ASICs, coarse-grained standard metal Structured ASICs, and field programmable gate arrays FPGAs.
  
  
• Stepping Up to PCI-Express (Oct. 06, 2005)
  LSI Logic
  
  
• A Complete Design Solution for Structured ASICs (Sep. 29, 2005)
  This whitepaper first summarizes the problems associated with conventional ASIC implementation technologies; next, introduces SA platforms and architectures; then describes the requirements for a true SA-capable design environment; and lastly, reviews arc
  
  
• Structured ASICs - A Risk Management Tool (Sep. 15, 2005)
  by Peter Woo, Senior Director of Product Marketing, eASIC Corp.
  
  
• PCI Express Design Considerations -- RapidChip Platform ASIC vs. FPGA Design Efficiency (Aug. 25, 2005)
  This paper describes the implementation differences of an IP core between FPGA and RapidChip® Platform ASIC technologies
  
  
• Structured Analog ASICs using the Mentor Graphics tool flow (Jun. 27, 2005)
  By James Kemerling, David Ihme and Clark Hopper - Triad Semiconductor, Inc.
  
  
• The Platform Based SOC Design that Utilizes Structured ASIC Technology (Jan. 28, 2005)
  The Platform Based SOC Design that Utilizes Structured ASIC Technology
  
  
• What platform ASICs are and when to use them (Jan. 10, 2005)
  What platform ASICs are and when to use them
  
  
• In-Depth: Making platform ASICs easier to use (Oct. 01, 2004)
  In-Depth: Making platform ASICs easier to use
  
  
• Trade-offs in high-performance comms (Sep. 13, 2004)
  Trade-offs in high-performance comms
  
  
• FPGA-to-ASIC conversion a crucial concern (Sep. 13, 2004)
  FPGA-to-ASIC conversion a crucial concern
  
  
• Platform ASICs stake the middle ground (Sep. 13, 2004)
  Platform ASICs stake the middle ground
  
  
• Structured ASICs take FPGA prototypes into volume production (Sep. 13, 2004)
  Structured ASICs take FPGA prototypes into volume production
  
  
• New Approach Combines ASIC and FPGA Benefits (Jul. 27, 2004)
  New Approach Combines ASIC and FPGA Benefits
  
  
• Build Complex ASICs Without ASIC Design Expertise, Expensive Tools - Take advantage of an architecture comparable to your original FPGA prototype design by migrating to a structured ASIC (Mar. 04, 2004)
  Build Complex ASICs Without ASIC Design Expertise, Expensive Tools
  
  
• Hybrid process converts FPGAs to structured ASICs (Feb. 12, 2004)
  Hybrid process converts FPGAs to structured ASICs
  
  
• Structured ASIC Based SoC Design (Jan. 30, 2004)
  Structured ASIC Based SoC Design
  
  
• Platform-based SOC Design: Point and Counterpoint (Jan. 22, 2004)
  Platform-based SOC Design: Point and Counterpoint
  
  
• Commentary: Fast ASICs with structure (by Clive Maxfield) (Oct. 31, 2003)
  Commentary: Fast ASICs with structure (by Clive Maxfield)
  
  
• Structured ASICs allow improved design flow (Oct. 24, 2003)
  Structured ASICs allow improved design flow