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Spi slave IP Listing

151 IP Cores (41 - 80)

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Express Serial Peripheral Interface IP Core

eSPI controller is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of standard eSPI specification. Through its eSPI compatibility, it provides a simple interface ...

41
OCTAL SPI Master IP

Octal SPI master is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of Macronix (MX66LM1G45G) Octal SPI REV.1.0 specification.Through its octal SPI master ...

42
eSPI Slave SOC IP

eSPI Slave SOC is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of standard eSPI specification. Through its eSPI compatibility, it provides a simple interface ...

43
SPI Master IP

SPI Master is full-featured, easy-to-use, synthesizable design, compatible with SPI Block Guide 4.01 Complient. Through its SPI Master compatibility, it provides a simple interface to a wide ...

44
xSPI Master IP | NOR IP

Arasan Chip Systems, the leading provider of IP for Mobile Storage Standards, presents its latest xSPI Master IP for access to NOR Flash Devices. This Universal NOR Flash IP supports a variety ...

45
I2C Slave with APB Master Bridge (I2C2APB)

The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

46
I2C Slave with AXI Master Bridge (I2C2AXI4)

The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

47
I2C Slave with AHB Master Bridge (I2C2AHB)

The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

48
SPI to AXI4 Controller Bridge

The SPI to AXI4 Controller Bridge IP core enables easy inter-chip board-level interfacing between virtually any microcontroller (MCU) and Xilinx Zynq-7000 AP SoC and FPGAs through the Serial ...

Get your evaluation logicBRICKS IP core here!

49
MIPI SPMI Slave IP

MIPI SPMI Slave interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI companilitity, it provides a simple ...

50
SPI Master - EEPROM Controller

The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can be programmed to run either in standard ...

51
High Speed SPI AHB IP Core- Serial Peripheral Interface

The Arasan High-Speed SPI - AHB IP Core provides a high-speed data communication channel between the AHB and SPI buses. The SPI - AHB bridge enables an AHB host to access a serial device at ...

52
QUAD SPI Memory controller

The core maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. Reading memory is performed by directly accessing the memory using reads on a AHB ...

53
SPI Master Serial Interface Controller

Master serial interface compatible with the popular SPI standard. Features a simple command interface and permits multiple SPI slaves to be controlled directly from your FPGA, CPLD or ASIC ...

54
Quad SPI Master IP

Arasan Chip Systems Quad SPI (QSPI) master core is easy to use, simple to work with, quick to operate, and reliable under all conditions. It supports the majority of QSPI devices standard from ...

55
FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)

The FSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clock signal (SCK). The FSPI system is flexible ...

56
Octal SPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) and DMA Support

Octal SPI master is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of Macronix (MX66LM1G45G) Octal SPI REV.1.0 specification. Through its octal SPI master ...

57
AHB Lite to SPI Bridge

The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol is implemented on the SPI bus. The ...

58
Dolphin SPI Controller

Dolphin Technology provides Serial Peripheral Interface (SPI) IP which enables an AHB/APB host to access a serial device at high-speed through the SPI interface. The controller supports both ...

59
Dolphin Octal SPI Controller

Dolphin Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with ...

60
Dolphin Quad SPI Controller

Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations. The Quad SPI IP either controls a serial data link as ...

61
I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface

The I2C Controller IP Core implements an I2C Slave Controller, with a user parameterized Register Array or Memory (i.e SRAM / FIFO) or any Peripheral connecting on an AHB / APB / AXI / Avalon ...

62
Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO

The Hs-Mode I2C Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or any Peripheral or CPU connecting through an internal AHB / APB / AXI / Avalon ...

63
SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)

The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex). The DB-SPI-M contains an ...

64
SPI Master Controller w/FIFO (APB Bus)

The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex). The DB-SPI-M contains an ...

65
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA

The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash Memory devices by way of Boot, Execute-in-Place ...

66
eSPI & SPI Master Controller w/FIFO

The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave ...

67
MIPI RFFE Slave IP

MIPI RFFE Slave interface provides full support for the two-wire MIPI RFFE synchronous serial interface, compatible with RFFE specification. Through its RFFE compatibility, it provides a simple ...

68
Quad SPI Master IP

QUAD SPI MASTER is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of SPI Vendor Specifications.Through its QUAD SPI compatibility,it provides a simple interface ...

69
Standard SPI Single Master

The Standard SPI Single Master is a single master controller and uses a message queue based architecture. A message consists of the command, transmit data and receive data field. The command ...

70
I2C Master/Slave Interface

CoreI2C provides an APB-driven serial interface, supporting I2C, SMBus, and PMBus data transfers. Several Verilog/VHDL parameters are available to minimize FPGA fabric area for a given application. ...

71
SDIO/SD Memory/MMC Slave Controller

The SDIO/SD Memory/MMC Slave Controller IP Core supports both 1 and 4 bit SD interface (up to 8 bits in optional MMC support) and SPI mode. Data rate of up to 25Mbyte/sec (200Mbs) can be realized ...

72
AXI Quad SPI

The AXI Quad Serial Peripheral Interface connects the AXI4 interface to those SPI slave devices which are supporting the Dual or Quad SPI protocol along with Standard SPI protocol instruction ...

73
DO-254 AXI Serial Peripheral Interface (SPI) 1.00a

Provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices. Not needed for Zynq unless >2 needed. Connects

74
Four-Wire slave IP for use with the Mentor M8051W and M8051EW

The M4WIS adds four-wire slave capability to the M8051W and M8051EW microcontroller designs that are compatible with the I2C Fast protocol. Clock stretching can be achieved under register control ...

75
SD Memory Slave Controller

The SD Memory Slave controller is designed to reside within SD Memory card. This slave controller provides simple and general-purpose 8-bit interface to user application. This controller handles ...

76
SDIO Slave Controller

SDIO Slave controller facilitates the design of SDIO cards and reduces the development time. By using this IP core, customers no longer need to spend time on handling the SD bus protocol since ...

77
MIPI I3C Slave Controller

The proliferation of sensors in mobile wireless and mobile-influenced products has created significant design challenges. Because there are no consistent methods for interfacing physical sensors, ...

78
Four-Wire Slave Interface for M8051W and M8051EW Microcontrollers

The M4WIS adds four-wire slave capability to the M8051W and M8051EW designs. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC SoC and FPGA designs. ...

79
DO-254 SPI Master

The SPI Master IP Core implements an SPI Master fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual). The Serial Peripheral Interface (SPI) bus is a synchronous serial ...

80

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