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Amba 4 IP Listing

551 IP Cores (241 - 280)

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MACsec Engine, 1G to 25G, Full Duplex, Integrated

As part of Rambus' award-winning silicon Intellectual Property (IP) product portfolio, the EIP-165 is a high-performance, split ingress/egress in-line MACsec frame engine that provides hardware ...

241
AES + SHA DMA Crypto Accelerator

The EIP-120 is a low-power low-gatecount crypto core with DMA capability and local key storage. Compared to a software only solution, the core provides higher performances and additional security ...

242
Secure-IC's Securyzr(TM) True Rendom Number Generator

The True Random Number Generator is an essential silicon-proven digital IP core for all FPGA, ASIC and SoC designs that targets cryptographically secured applications. It is a digital source ...

243

MIPI DSI TX Controller

The MIPI DSI Transmitter IP is an all-digital design consisting of a Redistribution Layer to interface to one or more Display Modules, external register interface for configuration of the Transmitter ...

244

Dual-Role Device Controller for USB 3.1

Compliant with USB Specification for SuperSpeed Universal Serial Bus version 1.0, The USB 3.0 Device Controller IP provides SuperSpeed USB (5 Gbps), High Speed (480 Mbps) and Full Speed (12 ...

245

USB 2.0 Controller

Certified for compliance with USB Implementers Forum Specification for Universal Serial Bus version 2.0, The USB 2.0 High Speed Device Controller IP provides USB High Speed (480 Mbps) and Full ...

246

RapidIO to AXI Bridge (RAB)

The RapidIO to AXI Bridge is a highly flexible and configurable IP used along with the native RapidIO Controller (GRIO) to provide RapidIO interface on one side and AXI interface on the system ...

247

32-bit Deeply Embedded Processor

The BA22-DE is a compact yet powerful 32-bit processor for deeply embedded applications. It is a Harvard-style processor able to run at relatively high clock frequencies (more than 800MHz in ...

248

32-bit Application Processor

The BA25 is a 32-bit processor for demanding systems running applications on general-purpose operating systems such as Linux and Android. The high-performance BA25 processor runs at high clock ...

249

ColdFire V1 Processor Platform

The ColdFire V1 Platform is a fully configurable microcontroller subsystem built from the same ColdFire V1 32-bit processor IP that is implemented in ColdFire+ family devices from Freescale ...

250

Mil-Std-1553B/AS15531 Interface

The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM). The core is connected ...

251

SpaceWire Routing Switch

The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard. The core is highly configurable, flexible and portable to a wide variety of ...

252

DES and Triple DES (TDES or 3DES) encryption and decryption coprocessor

The Triple DES Coprocessor is a Data Encryption Standard (FIPS 46-3) peripheral computing DES and Triple DES (TDES and 3DES) encryption and decryption through a highly-optimized secure architecture. ...

253

Hardware accelerator for RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms

The Public Key Cryptographic Coprocessor (PK2C) is a hardware accelerator intended to speed-up the core functions of public-key cryptography algorithms such as RSA, DSA, Diffie-Hellman, El-Gamal ...

254

ISO/IEC 14443 type A protocol manager for Proximity Integrated Circuit Card (PICC)

The ISO 14443 Type A Digital Controller is a fully integrated protocol manager intended for Proximity Integrated Circuit Card (PICC).

255

ISO/IEC 14443 type B protocol manager for Proximity Integrated Circuit Card (PICC)

The ISO 14443 Type B Digital Controller is a fully integrated protocol manager intended for Proximity Integrated Circuit Card (PICC).

256

ISO/IEC 7816-3 digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards

The ISO 7816-3 Integrated Circuit Card (ICC) Digital Controller is a fully integrated protocol manager intended for smart cards.

257

Display Controller - LCD / OLED Panels (AXI Bus)

The Digital Blocks DB9000AXI LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a LCD or OLED display panel. ...

258

Display Controller - LCD / OLED Panels (AXI4 Bus)

The Digital Blocks DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protocol Interconnect to a LCD or OLED display panel. ...

259

BitBLT Graphics Hardware Accelerator (AXI Bus)

The BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster ...

260

BitBLT Graphics Hardware Accelerator (AHB Bus)

The Digital Blocks DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen ...

261

BitBLT Graphics Hardware Accelerator (AXI4 Bus)

The Bit Block Transfer (BitBLT) Graphics Engine IP Core provides hardware acceleration of block moves with Raster Operation (256 data manipulation operations) of off-screen or on-screen data ...

262

Scalable 3D Graphics Accelerator

The logi3D graphics accelerator IP core is specifically designed for the new Xilinx Zynq-7000 All Programmable SoC. Designers can add attractive 3D graphics, including advanced Graphical User ...

263

Full HD/UHD multi-stream video and vision integrated platform solution

The full HD/UHD multi-stream video and vision platform integrates both full-HD/UHD multi-standard video codecs and embedded vision acceleration on a single silicon footprint with minimum load ...

264

Full HD video and vision integrated platform solution

The full HD video and vision platform integrates both full HD multi-standard video codecs and embedded vision acceleration on a single silicon footprint with minimum load on the host CPU. The ...

265

HD video and vision integrated platform solution

The HD video and vision platform integrates both 720p HD multi-standard video codecs and embedded vision acceleration on a single silicon footprint with minimum load on the host CPU. The integrated ...

266

MPEG-1/2 – Layer I/II Audio Decoder

The MPEG-1/2 – Layer I/II Audio Decoder (CWda75) is an audio IP core for decoding one audio stream in real-time. This core contains the MPEG-1/2 – Layer I/II decoder software and the Coreworks ...

267

Configurable UART with FIFO, hardware and software flow control

The D16752 is a universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs and automatic hardware/software flow control. It offers enhanced features, like transmission control register ...

5 Testimonials
Jian Gang, Technical Manager, State Nuclear Automation Instrumentation System Engineering Co., Ltd.

268

Constant False Alarm Rate Processor (CFAR)

The Constant False Alarm Rate (CFAR) core is a high throughput IP core, whose main application area is automotive driver assistance radar. It is normally applied post-FFT in order to scan output ...

269

NAND Flash Controller

• Specially designed for high performance with MTD Drivers Linux subsystem • Support for 8-bit NAND-Flash chips • Reading speed up to 40 MB/sec • Hardware checksum calculation ...

270

AXI External Memory Controller

The AXI EMC (Advanced Microcontroller Bus Architecture (AMBA®) Advanced extensible Interface (AXI) External memory controller) provides the control interface for external synchronous, asynchronous ...

271

AXI Interconnect

Included at no additional charge with Vivado and ISE Design Suite The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. ...

272

PLBV46 to AXI Bridge

The Processor Local Bus (PLB v4.6) to AMBA® (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. It ...

273

HyperLink High Speed DSP Interface Core

The HyperLink High Speed DSP Interface Core leverages the proven TI HyperLink technology connecting your FPGA design to a Texas Instruments C66X multi-core DSP at rates up to 25 Gb/s. An industry ...

274

PCIe DMA Controller (Low Latency)

The RapidDMA IP solution offers a fully integrated, highly-configurable, multi-channel and low latency PCIe-DMA solution. The IP solution is optimized for high performance and low latency and ...

275

32 bit Microprocessor compatible to ARMv7-m ISA (Cortex-M3)

compatible to ARMv7-M Instruction Set Architecture (Cortex-M3) ; single clock, static design ; single AMBA V2.0 AHB bus interface ; vectored interrupt controller ; enhanced instructions ; ...

276

AXI Protocol Checker

The AXI Protocol Checker core is designed to monitor AXI interfaces. When attached to an interface, it actively checks for protocol violations and provides an indication of which violation occurred. ...

277

AXI Virtual FIFO Controller

The AXI Virtual controller is provided under the terms of the XILINX End User License and is included with ISE® and Vivado™ design tools at no additional charge. Xilinx provides ...

278

AXI4-Stream Protocol Checker

The AXI4-Stream Protocol Checker core monitors AXI4-Stream interfaces for protocol violations and provides an indication of which violation occurred. The checks are synthesizable versions ...

279

SPDIF

Xilinx provides a SPDIF Controller to transport audio data. The Sony/Philips Digital Interconnect Format (SPDIF) core is a digital audio interface controller that implements the International ...

280

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