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Interface and interconnect IP Listing

428 IP Cores (1 - 40)

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AXI- Interconnect : Advanced Extensible Interface Bus IP

The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for high-speed submicrons interconnect.

1
Universal Chiplet Interconnect Express (UCIe) Controller

Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The IP also enables latency-optimized NoC-to-NoC ...

2
Serial Peripheral Interconnect Master & Slave Interface Controller

The SPI-MS core from Alma Technologies implements a Serial Peripheral Interconnect interface controller, which can operate either as a Master or a Slave. The Serial Peripheral Interface (SPI) ...

3
UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect

Blue Cheetah is a leader in Die-to-Die (D2D) interconnect solutions for chiplets in very advanced and low-cost packaging applications. BlueLynx™ is a revolutionary D2D subsystem architecture ...

4
Physical Layer Interface Core

Fully Compliant with Rapid Interconnect Specification Rev 1.1, 3/2001 prescribed by Rapid Trade Association. ; 32-bit standard Host/Link Interface. ; Full Duplex Independent Transmit and Receive ...

5
Low Latency Interconnect for AI/ML (GreenIPCore Shared Multi Memory Integration Controller (SMMIC))

Low Latency Interconnect for AI/ML developed with Advanced Low Power methods and Design Architecture solves Routing Congestion, Delay in Command priority and latency issues. Low Power Edge AI/ML ...

6
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC

This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5.1 interface spec. Lower power consumption is achieved due to ...

7
PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface

Rambus PCIe Controller IP for USB4 with AXI is a configurable and scalable PCIe controller Soft IP designed for implementations in USB4 devices. It supports the PCI Express 5.0 specification ...

8
Reduced Media Independent Interface (RMII)

The MII to RMII LogiCORE is a "shim" core which converts a traditional 16-pin Media Independent Interface (MII) on a Xilinx 10/100 Ethernet MAC core to a a 6-pin Reduced Media Independent ...

9
SPI-4 Phase 2 Interface Solutions

The Xilinx SPI-4 Phase 2 core provides a fully compliant Packet-Over-SONET/SDH (POS) solution, which can be quickly integrated into networking systems. Through user-configurable options, ...

10
AXI Interconnect

Included at no additional charge with Vivado and ISE Design Suite The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. ...

11
SelectIO Interface Wizard

The SelectIO Interface Wizard is provided under the terms of the Xilinx End User License and is included with ISE and Vivado software at no additional charge. Xilinx provides an ...

12

AXI4-Stream Interconnect

Included at no additional charge with Vivado and ISE Design Suite. Xilinx provides the AXI4-Stream Interconnect core which provides capability to connect multiple master/slave AMBA® ...

13

AXI4-Lite IP Interface (IPIF)

The LogiCORE™ IP AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of ARM® AMBA® AXI control interface compatible products. It provides a point-to-point bidirectional interface ...

14

PCIe - PCI Express Controller

Silicon Interfaces' PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard. ...

15

FlexNoC 5 Network-on-Chip (NoC)

Arteris FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of system-on-chip (SoC) devices for mobile, automotive, ...

16

FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.

For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required to meet the more stringent ISO 26262 ASIL ...

17

Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)

The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. ...

18

Universal Chiplet Interconnect Express (UCIe 1.0) Controller

Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller is a high-bandwidth, low-power and ...

19

ZLIB compatible compression and decompession, with DMA and AXi interface

This is a high performance, small footprint ZLIB compatible IP Core. It features 3 DMA engines, AXI interconnect and separate clocks for AXI interfaces and compression/decompression engines.

20

I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)

The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard ...

21

I2C Master / Slave Controller w/FIFO (APB Bus)

The I2C Master / Slave Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, ...

22

MIPI LLI Controller - (Low Latency Interface)

The MIPI LLI Controller IP Core resides on each instance of a chip pair, and the two controllers communicate at a physical level through the M-PHY and their associated differential signals. ...

23

I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)

The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard ...

24

PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface

Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is compliant with the PCI Express 3.1/3.0 ...

1 Testimonial
Murthy Kompella, VP of Engineering, Kazan Networks

25

PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect

Rambus PCIe 2.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controller with AXI is compliant with the ...

26

Local Interconnect Network (LIN) Soft Controller IP

The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, primarily designed to be used in automotive applications. Compared to the ...

27

AHB Multilayer Interconnect

The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fabric offers higher interconnect throughput ...

28

AXI Multilayer Interconnect

The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric offers high interconnect throughput, as ...

29

AXI Interconnect Fabric

The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5 channels (write address, read address, ...

30

I2C Slave Controller - Low Power, Low Noise Config with APB Interface

The Digital Blocks DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an ...

31

AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA

The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash Memory devices by way of Boot, Execute-in-Place ...

32

AHB Multilayer Interconnect IP

AHB AHB Multilayer Interconnect IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. AHB AHB Multilayer ...

33

USB OTG Function Controller

USB OTG Function Controller is a highly integrated USB OTG solution for USB OTG applications. SI22USBOTG11 is a USB OTG Function Controller Core designed as per USB OTG specification, which ...

34

OPB/PLB PCI32 Interface

The OPB to PCI 32/33 Bridge is offered as an evaluation core in the EDK. To generate a full OPB to PCI license, the PCI-32 LogiCORE must be purchased. The OPB IPIF/ V3 PCI Core Bridge ...

35

AMBA AHB-Lite Bus Interface

CoreAHBLite is a multi-master implementation of the AHB-Lite bus interconnect (a subset of the AMBA advanced high-performance bus) used to connect subsystem cores to Microsemi's 32-bit ARM processors. ...

36

XAUI 10Gb Ethernet Attachment Unit Interface

10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to drive up to 20 inches of PCB trace on standard FR-4 material. ...

37

DO-254 AXI Interconnect

Connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. Basically this block connects multiple external peripherals, like a big switch with an arbiter ...

38

AXI4 Interconnect

The AMBA AXI4 Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AMBA AXI protocol supports high-performance, high-frequency ...

39

Scalable Cache Coherency

Scalable cache coherency solution for many-core architecture: * up to 1024 fully coherent cores. * optimized protocol with false sharing prevention * configurable for heterogeneous ...

40

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