This is a self-contained configurable multi-port USB Type-C Power Delivery (PD) Design IP that is based on the latest USB Power Delivery specification revision 3.0 and USB Type-C Cable and Connector specification revision 1.2. This IP uses high performing customized 8-bit, 50-MHz MCU with configurable internal flash up to 72-KB, 8-KB SRAM, 24 GPIOs, an Authentication engine, and integrated VCONN FETs. Each port is independently capable of supporting Provider only, Consumer only, Provider/Consumer and Consumer/Provider PD Roles along with Type-C specific upstream-facing port (UFP), downstream-facing port (DFP) or dual-role port (DRP). The analog PHY portion detects and supports dead battery interacting with Power Management (PMIC) and Battery Charger (BC) ICs. This IP provides interface with system host to control and status update especially needed for System Policy Manager (SPM) communication. In addition, this IP supports advanced low-power management.
- I.Fully compliant with USB PD Specification revision 3.0 and Type-C Cable and Connector specification revision 1.2
- a) Completely self-contained (Embedded Controller (EC) less operation) configurable multi-port PD system.
- b) Multi-port(s) are managed under the control of Device Policy Manager (DPM) firmware stack running over MCU for PD negotiation across ports.
- c) Hardware implementation of Physical (PHY), Protocol and Policy Engine layers for power and area savings.
- d) System host control interface for System Policy Manager interaction.
- e) Integrated VCONN FETs with over current protection (OCP) and over voltage protection (OVP).
- f) Supports dead battery operation.
- g) Supports audio accessory, debug accessory and alt modes.
- h) Supports SOP* for communicating with EMC cable ICs, alternate modes and protocol adapters.
- II.Firmware configurability
- a) Role configuration for Provider (Source) only, Consumer (Sink) only, Provider/Consumer and Consumer/Provider for power.
- b) Vendor Defined Messages (VDM).
- c) Alt mode support for Display Port over Type-C.
- d) Framework to support wide range of Power Management Integrated Circuit (PMIC) and Battery Charger (BC) Ics
- e) Support for USB PD hardware layer bypass modes.
- III.8-bit MCU Subsystem
- a) 50-MHz High performing MCU.
- b) Configurable internal flash up to 72-KB.
- c) Configurable SRAM up to 8-KB in case of internal flash support.
- d) Integrated MUL and DIV blocks.
- IV.Integrated Digital blocks
- a) Common hardware Crypto block for authentication across multiple ports I2C, SPI and UART.
- Fully Synthesizable Verilog RTL source code
- Firmware source code
- ASIC / FPGA Synthesis constraints and scripts files
- FPGA Development platform kit
- Complete USB PD IP in GDSII including Analog PHY
- UVM based Verification Environment and test sequences
- User Manual, Programming guide and Verification documents
- Computing and smart phones
- Consumer electronics
- Power adapters and Banks
- Doc hub and cables
Block Diagram of the USB Type-C Power IP Core