D&R Headline News (Last 14 Days)

Headlines for Thursday May. 01, 2025

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Movellus Debuts Industry-First On-Die Power Delivery Network Analyzer

Aeonic Insight PDN IQ arms industry with unprecedented transistor-level PDN visibility and analytics that spans the entire product cycle from bench to in-field monitoring

• Weebit Nano Q3 FY25 Quarterly Activities Report
• Codasip launches complete exploration platform to accelerate CHERI adoption

Headlines for Wednesday Apr. 30, 2025

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Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs

Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that it has joined Intel Foundry Accelerator Ecosystem Alliance Program, as a member of both the IP Alliance and the recently announced Chiplet Alliance.

• VSORA Raises $46 Million to Bring World's Most Powerful AI Inference Chip to Market
• SkyeChip Joins Intel Foundry Accelerator IP Alliance
• Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
• Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
• Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
• CFX 0.13µm eFuse OTP IP has been applied in the mass production of over 15,000 CMOS image sensors

Headlines for Tuesday Apr. 29, 2025

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VeriSilicon Launches the Industry-Leading Automotive-Grade Intelligent Driving SoC Design Platform

The newly launched automotive-grade high-performance intelligent driving SoC design platform adopts a flexible, configurable architecture, supporting efficient collaboration among multiple co-processors, including high-performance multi-core Central Processing Units (CPUs), image signal processors, video codecs, and neural network processors.

• BrainChip Collaborates with Chelpis-Mirle on Security Solution
• Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC design migration
• Intel Foundry Gathers Customers and Partners, Outlines Priorities
• New Audio Sample Rate Converter (ASRC) IP Core from CAST Offers Versatility with High Fidelity

Headlines for Monday Apr. 28, 2025

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QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip

This milestone marks the first time eFPGA Hard IP has been delivered for a sub-5nm process node and is expected to set new standards for low power consumption, high performance, and optimal silicon area utilization (PPA).

• NEXT Semiconductor Technologies Collaborates with BAE Systems to Develop Next Generation Space-Qualified Chips
• Premier ASIC and SoC Design Partner Rebrands as Aion Silicon
• Baya Systems, Imagination Technologies and Andes Technology to Present on Heterogeneous Compute Architectures at Andes RISC-V CON Silicon Valley
• Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
• Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
• Wi-Fi 7 (802.11be) RF Transceiver IP Core Ready for High Speed Wireless Connectivity Applications

Headlines for Friday Apr. 25, 2025

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Crypto Quantique announces QRoot Lite - a lightweight and configurable root-of-trust IP for resource-constrained IoT devices

Crypto Quantique announces a new lightweight root-of-trust (RoT) IP block to enable security feature implementation in resource-constrained microcontrollers and IoT devices. Called QRoot Lite, the implementation complies to the Measurement & Attestation RootS of Trust (MARS) specification developed by the Trusted Computing Group (TCG) as a lightweight, hardware security IP block for measurement, storage and reporting to attest to the health and trustworthiness of embedded IoT devices and sensors.

• Arteris Wins Two Gold and One Silver Stevie® Awards in the 2025 American Business Awards®
• Faraday Adds QuickLogic eFPGA to FlashKit-22RRAM SoC for IoT Edge
• Xylon Introduces Xylon ISP Studio
• BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation

Headlines for Thursday Apr. 24, 2025

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TSMC Unveils Next-Generation A14 Process at North America Technology Symposium

A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. It is also expected to enhance smartphones by improving their on-board AI capabilities, making them even smarter. Planned to enter production in 2028, the current A14 development is progressing smoothly with yield performance ahead of schedule.

• Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
• Cadence Enables Next-Gen AI and HPC Systems with Industry's Fastest HBM4 12.8Gbps IP Memory System Solution
• S2C and Andes Technology Announce FPGA-Based Prototyping Partnership to Accelerate Advanced RISC-V SoC Development
• PQShield launches UltraPQ-Suite for deeply specialized implementations of post-quantum cryptography
• Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
• BrainChip Extends RISC-V Reach with Andes Technology Integration
• Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC's A16 and N2P Process Technologies
• Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
• M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation

Headlines for Wednesday Apr. 23, 2025

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Alphawave Semi Delivers Foundational AI Platform IP for Scale-Up and Scale-Out Networks

Alphawave Semi’s platform of ready-to-integrate subsystem IP for 64G UCIe, 224G SerDes, 800G/1.6T UALink and UEC plus reference chiplet architecture designs will underpin future AI deployments

• Crypto Quantique publishes independent cetome analysis on streamlining CRA compliance with the QuarkLink security platform
• DVB-S2X Wideband LDPC/ BCH Encoder FEC IP Core Available For Licensing and Integration From Global IP Core
• Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions

Headlines for Tuesday Apr. 22, 2025

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Ceva Neural Processing Unit IP for Edge AI Selected by Nextchip for Next-Generation ADAS Solutions

Nextchip license NeuPro-M NPU to bring powerful and highly efficient AI capabilities to boost performance and capabilities of automotive safety systems

• Cadence Advances AI in the Cloud with Industry-First DDR5 12.8Gbps MRDIMM Gen2 Memory IP System Solution
• Thalia joins GlobalFoundries' GlobalSolutions Ecosystem to advance IP reuse and design migration
• MosChip® to showcase Silicon Engineering Services at TSMC 2025 North America Technology Symposium

Headlines for Monday Apr. 21, 2025

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Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium 

Analog Bits will be demonstrating its newest LDO, power supply droop detectors, embedded clock LC PLL’s on the TSMC N3P process, and clocking, high-accuracy PVT and droop detectors on the TSMC N2P process at the Analog Bits booth at the TSMC 2025 North America Technology Symposium in Santa Clara, California.

• Alphawave Semi Audited Results for the Year Ended 31 December 2024
• BrainChip Gives the Edge to Search and Rescue Operations
• Shifting Sands in Silicon by Global Supply Chains
• Equal1 advances scalable quantum computing with CMOS-compatible silicon spin qubit technology
• New Breakthroughs in China's RISC-V Chip Industry

Headlines for Thursday Apr. 17, 2025

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VeriSilicon Launches Ultra-Low Power OpenGL ES GPU with Hybrid 3D/2.5D Rendering for Wearables

VeriSilicon’s GCNano3DVG IP combines optimized hardware pipelines with a lightweight and configurable software stack to deliver efficient, low-power graphics processing. It features separate rendering pipelines for 3D and 2.5D graphics, accelerating the rendering of complex scenes composed of 3D objects and vector graphics.

• JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
• BrainChip Gives the Edge to Search and Rescue Operations
• ASML targeted in latest round of US tariffs
• Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
• Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
• Secafy selects Siemens' EDA tools for innovative hardware security development

Headlines for Wednesday Apr. 16, 2025

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Cadence to Acquire Arm Artisan Foundation IP Business

The transaction will augment Cadence’s expanding design IP offerings, anchored by a leading portfolio of protocol and interface IP, memory interface IP, SerDes IP at the most advanced nodes, and embedded security IP from the pending Secure-IC acquisition.

• Orthogone Technologies and Blackcore® Technologies Announce Strategic Partnership to Deliver Ultra-Low Latency Solutions for High-Frequency Trading
• Intel Announces Strategic Investment by Silver Lake in Altera
• AMD Achieves First TSMC N2 Product Silicon Milestone