Atrenta Inc


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A consumer reports methodology for IP	May. 09, 2013

Guidelines for early power analysis	Feb. 11, 2013

Power awareness in RTL design analysis	Jul. 24, 2012

A practical approach to IP quality inspection	Sep. 27, 2011

SoC realization: Finally the "Killer App" that will allow EDA to grow again?	May. 16, 2011

Facilitating at-speed test at RTL (Part 2)	Apr. 21, 2011

Facilitating at-speed test at RTL (Part 1)	Apr. 18, 2011

Will IP use increase in forthcoming SoC design?	Nov. 04, 2010

Power analysis of clock gating at RTL	Jun. 14, 2010

Verification and Generation of Constraints	Aug. 10, 2009

Changing SoC Design Methodologies to Automate IP Integration and Reuse	Jul. 29, 2009

Measuring Quality in Semiconductor IP	Sep. 29, 2008

Preserving The Intent Of Timing Constraints	May. 19, 2008

Understanding Clock Domain Crossing Issues	Jan. 02, 2008

Timing Constraints Generation Technology	May. 24, 2007