D&R Industry Articles: SoC (System on Chip), Silicon IP, Semiconductor IP, Software IP, Verification IP, Core, Design Reuse


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Articles for the Week of Feb. 28, 2008



Featured Article Improving design turn around time on a complex SoC by leveraging a reusable low power specification This paper presents an approach to power design specification intent and associated enabled design methodologies that allow a scalable implementation of voltage islands.
Additional Articles
Dual Mode SMIA/MIPI Receiver Supporting 2Gbps
Power mode technologies verify today's SoCs
Multicore systems-on-chip can handle embedded designs
Complex SoC Testing with a Core-Based DFT Strategy
TI's MSP430 vs. ST Microelectronics' ARM Cortex-based processor for battery-powered apps
Signal Processing on the MIPS 74K


Articles for the Week of Feb. 21, 2008



Featured Article Secure Your Security Key in On-Chip SRAM: Techniques to avoid Data Remanance Attacks Security protection in modern microcontroller’s logic devices with memories is based on the assumption that information from the memory disappears completely after erasing or when the power to the memory is removed.
Additional Articles
Comparing IP integration approaches for FPGA implementation
Enhanced Capacitor Cross Coupled Front-End
ARM provides the microcontroller solution
Infusing Speed and Visibility Into ASIC Verification
Multi-language Functional Verification Coverage for Multi-site Projects


Articles for the Week of Feb. 14, 2008



Featured Article Building High-Quality, Mixed-Signal IP in 65-nm and Beyond This paper presents some key concepts necessary to design and build high-quality mixed-signal IP in 65‑nm or smaller geometries. The paper addresses design, layout, and verification techniques—with a focus on low-power design, reliability, and yield. Several design examples are presented, highlighting key techniques employed in the Synopsys® DesignWare® Mixed-Signal Intellectual Property (MSIP) portfolio.
Additional Articles
Designing digital video broadcast and wireless systems with common FPGA building blocks
Electronic system-level approach shortens SoC design
IPGenius, an on-line IP generation platform
Simplifying PLL Design
How to manage a billion cycles
Hardware design using ESL
Fast virtual platforms open up multicore software development


Articles for the Week of Feb. 07, 2008



Featured Article Accelerating High-Level SysML and SystemC SoC Designs The goal of this research is to analyze the mapping between SysML and SystemC, propose and suggest the SystemC modeling techniques that should result in modeling both the structure and behavioral SysML diagram to produce a single executable that represents the system behavior. A prototype for a translation tool, a SysML model compiler, has been implemented using a UML editing tool that supports SysML.
Software - The X factor
Using nextgen PCI Express switches to eliminate network I/O bottlenecks
Understanding the LIN PHY (physical) layer
Putting the system in electronic system design
DSPs vs. FPGAs for multiprocessing