Power has become a primary factor in the ever-important search for the “perfect” FPGA for a given design. Power management is critical in most applications. Some standards specify maximum power per card or per system. As such, designers must consider power much earlier in the design flow than ever before—often starting with the selection of an FPGA.
Research in 3D integration has been attracted researchers from industries as well as academics due to its superior benefits over 2D architecture such as better performance, lower power consumption, small form factor and support for heterogeneous technology integration. Depth understanding about 2D and 3D architecture is very important before real 3D design is taking place. In this paper, we discuss the research works on 3D integration particularly its benefits when comparing with CMOS scaling going to sub-nanometer process technology. We also describe several 3D architecture implementation previously developed to justify the need of our 3D experimental implementation which is currently being developed based on a long collaboration between ENSTA and GIPSA-Lab on multimedia MPSoC design.