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Infineon Technologies AG today announced it has demonstrated functionality and data rates exceeding 3.0 Gb/s speed of read channel, setting the pace for next-generation hard disk drive (HDD) System-on-Chip (SoC) technology
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Synopsys today announced that it has teamed with UMC to port the Synopsys DesignWare USB 2.0, PCI Express, SATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90-nanometer (nm) and 65-nm technologies
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During the demo, the PCIe link was established at 5 GHz and some of the industry’s best known companies were able to see measured simultaneous throughput of 350 MB/s (write to the server memory) and 380 MB/s (read to server memory)
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Faraday's DDR2 PHY IP, a reliable, cost-effective, and easy-to-integrate memory interface solution, enables semiconductor companies, in a timely manner, to make high performance DDR2 memory interface System-on-Chips (SoCs) for their consumer, automotive, industrial and medical applications
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PLDA Delivers PCI XpressLite Core for LatticeECP2M FPGAs; Partnership Focused on Expansion of Connectivity Solutions for Lattice Devices
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Freescale Semiconductor and STMicroelectronics have made significant progress in the areas of automotive IP development, flash technology alignment and new product definition
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Synopsys Leads Investment Along with Existing Venture Firms: Crescendo, TVM Capital and Ventech. Synopsys' investment was driven by the desire of both companies to lower the cost and risk of designing complex system-on-a-chip (SoC) integrated circuits and to foster industry-wide IP reuse capability. The Arteris NoC supports a wide array of IP protocols including ARM® AMBA® 3 AXI(TM), ARM AMBA 2 AHB(TM) and OCP(TM) protocols, which can be used concurrently without modification.
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Recognizing the semiconductor industry's need for an open market approach to providing comprehensive analog intellectual property (IP) solutions, Chipidea®, the world leader in analog/mixed-signal subsystems and IP, today announced it has created the first Analog IP Foundry(TM) to help customers circumvent the challenges of analog and mixed-signal design.
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New Products will Model and Simulate ARC Customers' Chips that Integrate ARC with Non-ARC Intellectual Property
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Jetstream Media Technologies announced today that the algorithms of its security IP cores have successfully passed the Cryptographic Algorithm Validation Program (CAVP), a strict governmental testing program for the validation of semiconductor algorithms
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ST confirms early availability of design platform for power-optimized System-on-Chip solutions, including 45nm libraries and first tape-out of 45nm SoC demonstrator IC
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IP Cores, Inc. announces an FPGA implementation of the AES Galois/Counter Mode (GCM) supporting the IEEE 802.1ae standard with real-life throughput exceeding 10 Gbps for all Ethernet frame sizes.
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By qualifying the NVM IP, a valuable memory addition to the foundry's IP Alliance Program, UMC's customers now have access to a low-cost, highly secure embedded NVM for applications such as electrical fuse replacement, flash and mask-programmable ROM replacement, code storage, RFID, unique ID, encryption, key storage, HDMI, and digital rights management (DRM).
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The IP business is ''broken'' and needs consolidation to better serve customers, according to Mike Kaskowitz, vice president of semiconductor IP at Mosaid Technologies Inc.
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StratiPHY3 intellectual property supports ADSL, ADSL2 and ADSL2+ as well as VDSL1 and VDSL2 and allows silicon providers to combine a complete, field-proven DSL solution with the strength and diversity of their own silicon product offerings to penetrate the world's largest broadband access market.
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Aart de Geus, chairman and CEO of Synopsys Inc. (Mountain View, Calif.), looks a decade ahead to discern the future direction of the EDA industry in an interview at this week's Design Automation Conference.
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Xerxes Wania, president and CEO of logic IP developer Sidense Corp. (Ottawa), spoke with EE Times editor-in-chief Brian Fuller at the Design Automation Conference.
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Adaptive Verification IP combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually. Adaptive Verification IP complements existing random or directed-random methods with a powerful new approach to reducing overall verification time, improving verification confidence, and enabling the explosion in SoC size and complexity to continue.
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Chipidea, the world's leading provider of analog/mixed-signal subsystems and intellectual property (IP), today introduced a new generation USB physical layer architecture using 1.8V IO devices that offers the industry's lowest power consumption for System-on-Chip (SoC) designs in the 65nm and 45nm advanced technology nodes.
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