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The new Xilinx 3GPP LTE Turbo Encoder and Decoder LogiCORE(TM) offerings deliver throughput speeds of up to 200 Mbps with the embedded digital signal processing (DSP) capabilities of Spartan(R) and Virtex(R) field programmable gate arrays (FPGAs)
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This new DDR3 DIMM offering adds unique capabilities in the memory controller and PHY IP that are needed for networking, storage and personal computing systems using DDR3 modules at data rates up to 12.8GBytes/s per DIMM.
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Supporting speeds of up to 1066 Mbps in 65-nanometer (nm) G processes, the all-digital Intelli DDR2/3 PHY+DLL achieves performance and resolution levels that were previously only possible with analog solutions.
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EVE, the leader in hardware/software co-verification, today announced availability of DW-FPGA, a DesignWare® foundation library for use with field programmable gate array (FPGA) synthesis software.
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This latest package release provides a complete and an accurate solution for simulating memories, including support for most of the memory technologies, including DRAM, SRAM, Flash, and Card memories, and several standard protocols.
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DoCoMo Capital Joins Existing Investors, Synopsys, Crescendo, TVM Capital and Ventech to Fund the Leading NoC Interconnect Solution Provider
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The new Audio Codec IP achieves an impressive 100dB dynamic range and -93dB THD while consuming only 7.8mW power when playing back through stereo line outputs at 48kHz.
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The Stratix IV family has up to 680K logic elements (LEs), 2X bigger than Altera’s Stratix III family, currently the largest FPGAs on the market. The HardCopy IV ASIC family offers equivalent densities as the Stratix IV devices and features up to 13.3 million gates.
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The new members of the Library include high-performance transaction-level models (TLMs) for PowerPC®, MIPS, and DesignWare IP. DesignWare System-Level Library models significantly reduce the time to create virtual platforms and are written in SystemC to work in any IEEE 1666 (SystemC)-compliant simulation environment.
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Faraday Technology today announced that it has successfully integrated a hardened 533Mhz ARM(R) compliant core -- FA626 in a complex 130nm SoC ASIC for Radioframe Networks.
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The first platform, Taurus, which is targeted for access applications, provides programmability, flexibility and cost effectiveness unsurpassed in the market. Taurus includes a targeted set of access interfaces, including GPON, Ethernet, and POTS/TDM.
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The new VLSI test lab will provide analysis of VLSI libraries and ARM® physical IP to correlate design to silicon behavior. This activity has increasingly become a Partner requirement prior to SoC tapeout as technologies have increased in complexity and mask costs have escalated.
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Word on the street is that there is still a little more light to be shed on the saga of P.A. Semi and Apple.
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Allegro’s H.264 IP core is a real-time hardware encoder targeting mobile phones, camcorders, set-top boxes, webcams and video surveillance applications. Allegro’s IP core can process images up to high-definition resolutions.
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Having embarked on a restructuring of its physical intellectual property division (PIPD), processor licensor ARM Holdings plc (Cambridge, England) is now moving on to restructure its development systems business, according to Warren East, CEO and president.
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NXP Semiconductors is looking seriously at licensing to other semiconductor companies its Mifare contactless chip card platform technology for use in SIM cards and NFC applications such as ticketing, payment and access management.
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Revenue for the third quarter was $27.3 million, an increase of 3 percent over the prior quarter revenue of $26.5 million and an increase of 43 percent from the $19.1 million reported in the third fiscal quarter a year ago. Q3 revenue growth was driven primarily by increased license fees.
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