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MoSys today announced the availability of its silicon-proven DDR3 and DDR3/2 combo PHYs. MoSys’ fully-integrated solution complies with the latest DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3/2 DRAM devices.
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The two companies reveal today their agreement, whereby the fast growing Chinese embedded microprocessor supplier, Ingenic, has licensed the ultra-low power audio converter from the mixed signal Silicon IP provider, Dolphin Integration.
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Imagination Technologies has created a new class of embedded Connected Processor™ solutions that will power the ‘Internet Everywhere’ generation of consumer electronics.
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Digital Media Professionals today announced "SMAPH-S", a next generation OpenGL ES 2.0 shader-based graphics IP core. DMP will start providing the core to initial customers in 1Q 2010.
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Arasan Chip Systems today announced that Comsys Mobile has taken a license for Arasan's SDIO Version 2.0 Device IP Core, which supports a wide range of portable low-power applications such as 802.11 devices, GPS, WiMAX, UWB, among others.
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Open Core Protocol International Partnership (OCP-IP) today announced that OCP 3.0 specification has completed member review and is now the official specification of record. This latest version contains extensions to support cache coherence and more aggressive power management, as well as an additional high-speed consensus profile and other new elements.
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Imagination Technologies announces POWERVR VXE380, the latest member of Imagination’s third generation video encoder IP family, which delivers multi-standard encoding of video, now including H.264 High Profile (HP), at HD resolutions.
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Rapid Bridge announced today that it has taped out the world’s smallest USB 2.0/3.0 PHY. The USB 2.0/3.0 PHY is the newest member of Rapid Bridge’s LiquidPHY™ product family.
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Tiempo is demonstrating at the “Cartes 2009” event how its asynchronous design technology can dramatically improve processing speed for contactless applications with, as an illustration, a live demo of a secured PayPass™ transaction in which processing speed on the card is six times faster than industry implementations, showing a complete transaction in less than 60 ms.
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The patented Cassiopeia architecture for single via programmable ROM is enriched with a capability to operate from nominal voltage down to 1.1 V , both +/- 10%, in the TSMC 130 nm LP process.
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Intel and AMD today announced a comprehensive agreement to end all outstanding legal disputes between the companies, including antitrust litigation and patent cross license disputes.
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In just one day alone, China's SMIC suffered three major setbacks. On Tuesday (Nov. 10), it lost a big patent suit, its chief executive, and, in some respects, its independence.
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GigOptix, a leading high speed analog semiconductor manufacturer specializing in electronic engines for the optically connected digital world, today announced that the company has signed a definitive agreement, and completed the acquisition of ChipX, Incorporated, a privately-held fabless supplier of analog and mixed signal custom Application Specific Integrated Circuits (ASICs) on November 9, 2009.
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Arteris today announced the availability of two new on-chip interconnect products, the FlexNoC and FlexWay packages. With these offerings, Arteris expands the capabilities of its market-leading NoC Solution to address the complete range of SoC design styles, sizes and complexities.
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Traditional cache controllers are offered to improve the system frequency, involving a CPU and its program memory. But these caches are not concerned with power consumption. As a consequence, these solutions do not fit applications targeting low power. To bridge this gap, Dolphin Integration offers a new breed of cache controller: I-Stratus-LP.
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ARC Configurable 32-bit Processor Cores and Vertical Application Solutions Complement Virage Logic's Broad Portfolio of Semiconductor IP and Offer SoC Designers a Single Source for Highly Differentiated IP
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Sonics said today that Toshiba has licensed SonicsSX, a high-performance on-chip network, targeted at video-based SoCs (system-on-chips). This latest license represents an extension of Toshiba’s adoption of Sonics’ technology for its next-generation SoC designs.
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ASICS World Services, LTD. today released it's USB 3.0 Device IP Core. The USB 3.0 Device IP Core, supports SuperSpeed transfer speeds of 5Gbit/sec., and can be implemented in any technology, from FPGA to full custom ICs. Direct support is provided for Xilinx Virtex 5 FPGA with GTX transceiver, offering a true single chip solution, without the need for external PHYs. This IP Core also features an industry standard PIPE PHY interface for integration with 3rd party PHYs.
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MoSys today announced the availability of its PCI Express 2.0 PHY. MoSys' PHY complies with the PIPE 2.0 specification and provides the physical layer (PHY) interface that connects to industry standard PCI Express 2.0 controllers.
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