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Innopower, a wholly owned subsidiary of Faraday Technology, today announced, effective immediately, that it has been granted as the sole IP distributor of Faraday. Innopower will promote Faraday IP solutions in world-wide region and provide the front-line support for customers.
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MIPS Technologies today announced that Magic Pixel has licensed the MIPS32(R) 24KEc(TM) and 4KEc(R) Pro Series(R) processor cores for development of next-generation digital photo frames (DPFs) and other portable multimedia applications.
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MIPS Technologies and Tensilica today announced they are working together to accelerate SOC (system-on-chip) design activity on the popular Android platform. Together, MIPS and Tensilica will help companies speed the design of new home entertainment and mobile consumer products based on Android.
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Aptina and eASIC today announced the immediate availability of a H.264 High Definition (HD) reference design that is capable of supporting up to 720p/30fps rates. The HD H.264 reference design is built using Aptina’s MT9D131 HD image sensor with eASIC’s eDV9200 low cost HD H.264 CODEC.
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Silicon Image today announced the newest member of its IP core family, the cineramIC™ 4K and 3D H.264 digital video decoder. With its high performance, low cost and high-quality video imaging, the cineramIC IP core can be integrated into System-on-Chips (SoCs) for next-generation digital TV (DTV), set-top-box (STB) and camcorder applications, as well as professional video editing, broadcast, medical and surveillance FPGA applications.
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CEVA and Snowbush today announced that they have partnered to deliver a complete Serial Attached SCSI (SAS) 2.0 IP solution optimized for embedded storage applications. The integrated offering combines Snowbush silicon-proven 6.0Gbps PHY IP integrated with CEVA's SAS 2.0 Controller IP, offering the industry's most mature and feature rich SAS 2.0 IP solution.
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As recently as five years ago, ARM's competitors included a host of IP processor companies such as MIPS, ARC and Tensilica. Now, like it or not, the field of serious processor competition has dramatically narrowed to, well, ARM vs. Intel Corp.
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Denali today revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower.
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Mixel announced today the availability of the first MIPI/MDDI unified PHY IP solution. The IP combines a MIPI D-PHY compliant with revision 1.0 of the MIPI standard, with an MDDI-PHY compliant with revision 1.2 of the MDDI standard.
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Xilinx, Inc. today announced six new development kits as part of its Targeted Design Platforms for enabling developers to focus on innovation and differentiation when designing with FPGAs.
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Arteris announced today that it has raised the first tranche of a strategic investment round totaling $9.7 million from a group of investors led by Qualcomm Incorporated and including ARM.
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Is fabless still fabulous? In a panel session at the IP-ESC 2009 Conference this week in Grenoble, France, panelists discussed the evolution of semiconductor business models and confronted views on whether the fabless model is dead or alive and kicking.
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Novocell today announced the development of 2nTP, a new multi-time programmable (MTP) technology that allows the programming of its one-time programmable (OTP) antifuse bit cell up to eight (8) times. 2nTP can be configured as a two, four, or eight times write, and it is based on the NovoBlox™ bit cell, a non volatile memory (NVM) already proven at leading foundries.
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In a keynote at the IP-ESC 2009 Conference this week in Grenoble, France, Eric Schorn, vice president of marketing, processor division ARM Ltd, compiled a How-To list of basic steps to optimize IP business models and better deliver value to the customer.
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