Top Story
Pact XPP, a developer of a reconfigurable highly parallel processor architecture, has filed a law suit against FPGA vendor Xilinx Inc. and distributor Avnet Inc. in the Eastern District court of Texas, claiming patent infringement.
Top Story
Inicore Inc. announced today that Surrey Satellite Technology Limited in Guildford, UK, has licensed its Controller Area Network Intellectual Property core CANmodule-IIx for their new SGR-05P range of space-borne GPS receivers.
Top Story
Word on the street is that Imagination Technologies Group plc, licensor of graphics processor cores, has added Sony to its tally of international electronics systems company licensees.
Top Story
Tiempo today announces its new chip, fully operational at first run, that silicon-proves its 16-bit microcontroller core IP – TAM16 – on a CMOS 130 nm general-purpose process. The chip logic has been entirely designed in Tiempo’s innovative asynchronous and delay insensitive technology.
Top Story
Socle Technology Corp, one of the world’s leading-edge providers of SoC design, is first member of ARM’s IP Portfolio Program which enables fabless design houses to exploit the widest range of ARM technology as part of a full turnkey service.
Top Story
Imagination Technologies announced today the availability of two new IP cores in the POWERVR™ VXE video encoder family. POWERVR VXE251 and VXE280 deliver multi-standard encode at SD and HD resolutions respectively
Top Story
GDA Technologies announced plans today to ship “Pravega”--its USB 3.0 family of cores consisting of a highly configurable Superspeed device and host controllers that are interoperable with third party USB 3.0 PHY’s running at 5 Gbits/s maximum speeds.
Top Story
Cadence Design Systems today announced the planned first quarter 2009 availability of new Open Verification Methodology (OVM) verification IP (VIP) for two key high-speed protocols: USB 3.0 and PCI Express 3.0.
Top Story
Faraday Technology and Fresco Logic today announced a partnership to validate the integration of Faraday's USB 3.0 (SuperSpeed USB) PHY IP (Physical Layer IP) with Fresco Logic's USB 3.0 xHCI Host and Device Controller IP.
Top Story
PLDA today announced the immediate availability of a new line of SuperSpeed USB IP products designed for ASIC and FPGA.
Top Story
Synopsys today announced a complete, single vendor SuperSpeed USB IP solution consisting of the DesignWare® device controller, PHY and verification IP.
Top Story
SideWorks™ creates breakthrough in addressing Audio and Video applications in demand of area-optimized, performance and optimal power consumption
Top Story
Denali today announced that its PureSpec™ verification intellectual property (VIP) product now supports the USB 3.0 specification from the USB 3.0 Promoter Group , allowing device and system designers to begin advanced USB 3.0 development.
Top Story
The complaint seeks an exclusion order barring the importation, sale for importation, or sale after importation of products that infringe nine Rambus patents from the Ware and Barth families of patents.
Top Story
The company expects to eliminate at least 625 full-time positions, representing 12% of its global employee base, plus a substantial number of contractors and consultants.
Top Story
The co-operation enables IC designs and IP to be ported to a manufacturing standard in just a few weeks, typically offering upto 10X reductions in cycle time and engineering costs as well as freeing up customer’s engineers to focus on other potentially higher value added activities.
Top Story
Support for MMC 4.2 guarantees the IP core’s compatibility with the newest MMC-Plus memory cards, and thus increases the maximum data transfer rates to 400 Mbit/s.