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Rambus today announced that its customers have shipped over 50 million XDR DRAM devices worldwide.
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Rambus today announced that the jury in the case involving Hynix Semiconductor, Micron Technologies, and Nanya Technology Corporation has found in favor of Rambus.
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Sandia National Laboratories demonstrated this rapid turn-around for radiation-hardened (rad-hard) designs, using its ViArray trusted structured ASIC implementation platform based on ViASIC’s patented standard metal configurable fabric and Sandia’s radiation-hardened technology.
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Arasan announced today that its silicon proven Gigabit Ethernet IP solution has completed interoperability testing at the University of New Hampshire's Interoperability Lab (UNH IOL).
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The new node supports a performance-driven general purpose (40G) technology and a power-efficient low power (40LP) technology. It features a full design service package and a design ecosystem that covers verified third party IP, third party EDA tools, TSMC-generated SPICE models and foundation IPs. First wafers out are expected in the second quarter of 2008
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Under the terms of the agreement, Synopsys will pay $8 cash per Synplicity share, resulting in a gross transaction of approximately $227 million, and approximately $188 million net of cash acquired
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At the heart of the kit are Altera’s Cyclone® III FPGAs, which are an ideal video processing platform given the device’s large parallel processing capabilities with up to 288 multipliers, 4-Mbit embedded memory blocks, and low power consumption.
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Mentor Graphics today announced the immediate availability of a new version of Platform Express™ with full support for the IP-XACT 1.4 IP databook specification, new mixed-level RTL and ESL design capabilities, and a new portable generator format.
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The new offering will include Silvus' 802.11n PHY and Ittiam's 802.11n MAC. Highlights for this new joint offering include 20 MHZ and 40 MHz advanced MIMO modes and a 600 Mbps full throughput Media Access Controller (MAC) which is IEEE 802.11n draft 2.0 compliant.
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eASIC today announced it has raised $48M in late stage financing. The financing round was lead by Advanced Equities Incorporated.
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MIPS Technologies today announced that its 96dB Audio IP Codec -- already silicon-proven in multiple deep submicron processes and foundries -- has been silicon-proven in TSMC 90nm and Chartered Semiconductor Manufacturing 130nm processes.
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The ARC® Energy PRO™ core family leverages the company's recently announced, ultra low power Energy PRO technology to set new standards for low power consumption by reducing power usage by up to 75 percent
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CEVA's fully programmable, multi-standard multimedia platform now supports H.264, MPEG4, DivX, RealVideo, H.263, VC-1 and AVS video codecs
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The two new system IP products combine IP cores for an 8051 processor with an Ethernet MAC controller core and with a hi-speed USB 2.0 device controller core. Verified TCP/IP and USB software stacks are also included, and a development board is available for each subsystem.
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ZeBu-Personal shortens time to tapeout, improves product quality and eliminates costly respins, while accelerating software development ahead of silicon.
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Sidense announced today that it has raised $6 million in a venture capital financing round co-led by Vertex Venture Capital, a leading Israeli venture capital firm, and Tech Capital Partners of Waterloo, Canada.
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Xilinx today announced availability of a free hardware-verified reference design and 3rd party IP for the optical internetworking forum (OIF) SERDES framer interface level 5 (SFI-5) standard.
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Mixel is licensing its high performance LVDS De-Serializer transceiver IP to Faraday for use in their customer ASIC designs. The IP is designed in UMC 90nm process technology. This is intended to be the first of many IP development collaboration between Faraday and Mixel.