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Targeting next-generation Hi-Fi audio applications, the CEVA-TeakLite-III inherently supports 32-bit data processing functions with multiple precision points and offers an enlarged 64-bit data memory bandwidth. A FFT accelerator further boosts audio performance and reduces power consumption. For example, a 7.1 channel Dolby Digital Plus decoder would consume only 15% of the core's available MHz at a 90nm process, compared to 47% for its predecessor, the CEVA-TeakLite.
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The DesignWare SATA AHCI core is compliant with the SATA 2.6 specification and AHCI 1.1 specification, and includes an ARM AMBA 2-compliant subsystem interface. The DesignWare SATA AHCI core has been verified against the industry-standard AHCI software drivers provided as part of the Linux® and Windows Vista™ operating systems.
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Silicon Image today announced that by combining its digital implementations of the HDMI IP cores with its HDMI analog physical layer (PHY) semiconductors, the company has begun to achieve significant market success, having already sold approximately four million HDMI PHY semiconductors.
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The PLDA PCIe Gen 2 demo will include a FPGA-based board running PLDA's PCIe Gen 2 XpressRich IP on a server Platform featuring two quad processors from the industry leading processor manufacturer.
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The SATA PHY IP core, targeted for the TSMC 130nm Low Voltage Oxide (LVOD) process, provides a completely integrated solution for both SATA host and device applications running at either 1.5Gbps or 3.0Gbps speeds.
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Implemented in the 65-nanometer (nm) Common Platform process, Synopsys' DesignWare PHY for PCI Express and digital controllers are the first 65-nm IP to pass the PCI Express 1.1 compliance testing by the PCI-Special Interest Group (PCI-SIG(R)). Additionally, Synopsys' DesignWare USB 2.0 nanoPHY IP in the Common Platform 90-nm process is the first implementation to have earned Hi-Speed USB 'On-the-Go' (OTG) logo-certification by the USB Implementers Forum for devices manufactured at multiple foundries using a single GDSII source.
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The PCI Express Generation II product from PLDA features double the transfer speed – up to 5Gb/s – while maintaining the same quality, backward-compatibility, and ease of integration inherent in PLDA's PCI Express products. A complete test chip for PLDA's Generation II IP will be available to third parties beginning Q1 2008.
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STMicroelectronics, Intel and Francisco Partners today announced they have entered into a definitive agreement to create a new independent semiconductor company from the key assets of businesses which last year generated approximately $3.6 billion in combined annual revenue.
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With CHAINarchitect, chip architects can easily explore new interconnect topologies and perform ''what if'' analyses to optimize on-chip communications (bandwidth and latency) between IP cores along with overall system characteristics such as power, die area, system-level performance and others.
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Based on cryptographic research into ''side channels'' DesignTag is a small, low power, active digital circuit supplied as an IP core for inclusion in larger designs. The presence of DesignTags can be detected by a sensor placed in contact with the package of the chip which contains them. DesignTag communicates a unique tag to the sensor which can then be used to access information on the tagged product in a web-based database.
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Denali's Databahn PCIe IOV cores and PureSpec PCIe verification IP products provide full support of the Address Translation Service specification, Single-Root I/O Virtualization specification, including physical and virtual function (VF) configuration spaces, VF Alternate Routing-ID, and Functional Level Reset (FLR) capabilities.
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Denali's Databahn solutions aid BroadLight's developers to quickly design and verify DDR memory systems that meet or exceed OEM high-speed PON design requirements and time-to-market windows.
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Synopsys' industry-leading USB 2.0 nanoPHY mixed-signal IP, now available in the TSMC 65-nm process nodes, uses half the power and die area compared to previous USB solutions and enables faster time-to-market and reduced risk.
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The enhanced 360 MV supports the verification of IP with configurable functionality, such as optional memory-management units, or configurable synchronous or asynchronous FIFO implementations, and configurable dimensions, such as configurable bus-widths, FIFO depths, or register counts
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Duolog Technologies today announced the tape-out of a 0.13um IEEE 802.15.4/Zigbee radio test chip as part of their 802.15.4 transceiver development program.
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Lightspeed Logic's Reconfigurable Logic delivers a density and performance breakthrough for mask reconfigurable solutions, achieving 80% the density of traditional methodologies for multi-million gate logic blocks, twice the density of competing mask reconfigurable solutions.
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Effective immediately, MOSAID has the exclusive right to sub-license more than 50 LSI patents relating to memories, digital signal processors (DSPs), microprocessors, application specific integrated circuits (ASICs), and semiconductor processing technology.
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HLNAND Flash is a high-performance solution that combines MOSAID's own HyperLink memory technology with industry standard NAND Flash cell technology to deliver the industry's most advanced feature set, reaching sustained I/O bandwidths more than ten times higher than conventional Flash
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Engineers who are thinking of launching a silicon intellectual property (IP) business in their garage with a couple of friends had better think again, according to panelists at this week's EDA Consortium meeting. The overall message: it's a big business for big players now.
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STMicroelectronics today revealed the industry's first successful fabrication of the next- generation 65nm serial-interface MIPHY (Multi Interface PHY) Physical Layer interface IP (Intellectual Property). ST designed the macro-cell to be integrated with other functions into low power System-on-Chip (SoC) devices supporting both 3 Gbps and 6 Gbps Serial ATA (SATA) hard disk drives (HDDs) for mobile and desktop computing applications.
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Future Waves will market SoCs integrating Imagination's IP alongside Future Waves' leading multi-standard RF technologies to enable a range of mobile broadcast devices.
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