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Synopsys DesignWare® IP is architected for low power consumption in both active and standby modes. This is achieved by using power-efficient transmitters, phase-locked loop (PLL) blocks and clock gating techniques. Synopsys' USB 2.0 nanoPHY, designed for the latest mobility devices, consumes half the power of previous USB implementations. The PCI Express™, Serial ATA (SATA), and XAUI high-speed serializer/deserializer (SERDES) PHY IP support low-power modes and consume significantly less power than similar IP on the market.
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The first-ever multiple-time-programmable (MTP) NVM IP qualified and released for production at the 90-nanometer process node, Impinj's AEON/MTP cores provide the cost, power and functionality benefits of embedded NVM in standard logic CMOS (also known as Logic NVM.)
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eASIC today announced the availability of the H264-MCE multi-channel baseline video encoder core from CAST, Inc. for implementation in Nextreme Structured ASIC devices. This Intellectual Property core, which was proven in a 90nm Nextreme fabric, demonstrated 150MHz performance and is now offered as a low-cost and fast turnaround solution for a wide range of video processing applications.
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Mentor Graphics today announced a technology launch of subsystem intellectual property (IP), beginning with the industry's first USB subsystem solution from a single-source EDA provider. Mentor Graphics is the only EDA company that develops its own digital controller, hardware PHY (physical layer), and embedded software IP to deliver an integrated and verified IP solution for today's complex electronics designs.
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Agere Systems signed a new license agreement for Silicon Hive's HiveFlex CSP 2000 Series application specific communications processors. Agere's Telecommunications & Enterprise Networking business unit is using the HiveFlex CSP 2000 processor in communications applications.
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Jetstream Media Technologies announced today the availability of three IP cores: modular exponentiation accelerator, ultra fast XTS IP, and ultra-fast dual-mode JetCombo-2 IP.
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The ARM Cortex-M1 processor extends the range of the ARM Cortex processor family and enables OEMs to standardize around a common architecture across the performance spectrum. Actel has worked with ARM as lead Partner and is the first licensee of the Cortex-M1 processor for use by their FPGA customers
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S2C will provide CAST customers in China with a secure evaluation platform for IP reference designs using S2C's innovative FPGA-based ESL products. The CAST H.264 encoder core reference design is already available on the S2C TAI Logic Module(TM), a scalable rapid FPGA prototyping module. S2C plans to make more CAST IP available in the future.
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Faraday provides high performance 32-bit RISC CPU-based audio solutions, FIE7020 platform, which supports NAND flash/SD MMC card/HDD-based audio solutions with add-on video playback functions.
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SNOWBUSH's 1.0-5.0Gbps multi-standard SerDes macro provides a complete physical media attachment layer for PCI Express, SATA, SAS and Fibre Channel serial interconnects, and supports XAUI, Rapid I/O, Gigabit Ethernet and Infiniband.
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Lattice Semiconductor today announced the immediate availability of the industry's first 533 Mbps Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) controller Intellectual Property (IP) core supporting a Low-Cost Field Programmable Gate Array (FPGA) family. This DDR2 SDRAM IP core is optimized for Lattice's award winning LatticeECP2 and LatticeECP2M LatticeSC Extreme Performance FPGA family.
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The new products available include the Display Serial Interface (DSI) IP Core, the Camera Serial Interface (CSI-2) IP Core, and the D-PHY IP Core. The SLIMbus(TM) IP Core (Serial Low-power Inter-chip Media bus) supporting the preliminary draft specification is also available.
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The Endpoint IP enables high performance Serial RapidIO system interconnect between processors, bridges, remote memories, customer defined endpoint devices and Tundra RapidIO switches. The IP is compliant with RapidIO Interconnect Specification (Revision1.3) and supports up to 10 Gbps payload. Fully synthesizable, the IP is designed to be combined with technology specific SerDes on multiple process technologies.
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SafeNet today announced that it has entered into a definitive agreement to be acquired by an investor group led by Vector Capital in a transaction valued at approximately $634 million
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ARM today announced the ARM® Mali™ Software Development Kit (SDK), which enables game developers to quickly transition from generic application development to ready-to-use designs for a wide range of handsets. The Mali SDK enables developers to create and test games before silicon exists, thereby ensuring that new games are available on the day the handset is released and maximizing the time for which their games are marketable.
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Dolphin Integration has just released a Second Generation of audio CODECs offering a wide set of features and lowering integration costs. With an SNR at system-level measured at 90 dB, Dolphin's CODEC Best-in-class audio quality was already preferred by diverse Golden Ears finding it at par with the top external codec IC's
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