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Cadence today announced TripleCheck IP Validator, a new addition to the Cadence Verification IP (VIP) Catalog that simplifies and accelerates compliance testing of interface design IP. The expanding Cadence VIP Catalog is helping leading system and semiconductor companies quickly and thoroughly verify their implementations of standard interfaces, such as PCI Express 3.0.
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Applied Micro today announced the world's first web server implementation running on a 64-bit ARM v8-compliant processor.
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GLOBALFOUNDRIES today announced a significant milestone on the road to enabling 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, NY, the company has begun installation of a special set of production tools to create Through-Silicon Vias (TSVs) in semiconductor wafers processed on the company’s leading-edge 20nm technology platform.
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It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.
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ARM Holdings plc announces its unaudited financial results for the first quarter ended 31 March 2012. Total dollar revenues in Q1 2012 were $209.4 million, up 13% on Q1 2011. Q1 sterling revenues were £132.5 million, up 14% year-on-year.
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Chips&Media today announces that it has begun shipping the fully verified CODA9A0 video encoder and decoder IP to partners including Freescale, and it will be deployed in future i.MX application processors after i.MX6.
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The problems acknowledged by Qualcomm Inc. in getting enough 28-nm chips out of its foundry partner Taiwan Semiconductor Manufacturing Co. Ltd. are not about to prompt the company to build or acquire its own fab, according to Steve Mollenkopf, chief operating officer of the fabless chip company.
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TSMC will offer only one process at the 20-nm node, a change from the multiple processes that the foundry giant has offered customers for the past several nodes, a TSMC executive said Tuesday (April 17).
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Built on the proven foundation of the widely-used CEVA-TeakLite family, the CEVA-TeakLite-4 introduces innovative smart power management technology and supports customer-owned extensions, making it a highly flexible architecture and ideal for even the most area and power sensitive designs.
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MIPS Technologies Inc., a pioneer of the reduced instruction set computing (RISC) style of architecture, is looking for a buyer according to a Bloomberg report that referenced unnamed sources.
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MediaTek today approved the purchase and acquisition of the Swedish company Coresonic AB, a global leader of Digital Signal Processor (DSP) technology. Following the formalization of the acquisition, Coresonic AB will become another wholly owned subsidiary of MediaTek in Europe.
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Although only 2% growth was registered in the worldwide semiconductor market in 2011, several companies posted results that were far different.
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HDL Design House, a company that offers design and verification services as well as soft and hard IP cores (digital and analog), today announced the availability of soft IP TX and RX controller cores for the HDMI and DisplayPort standards.
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ARM, Gemalto and Giesecke & Devrient today announced the creation of a joint venture dedicated to delivering a secure, accessible environment for advanced services running on the growing range of connected devices.
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Open-Silicon announced today version six of the company’s Interlaken IP core. This release offers tremendous implementation flexibility to customers by supporting SerDes data rates up to 28Gbps and multiple data width options. The IP core also conforms to the recently released “Interlaken Retransmit Extension” protocol definition from the Interlaken Alliance.