Tensilica DSP IP supports efficient AI/ML processing
Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
Low Power Dual PHY for UCIe low cost robust Chiplets
TSMC 3nm (N3E) GPIO Basekit Libraries
TSMC plans 1.6nm process for 2026
Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Embracing a More Secure Era with TLS 1.3
Maximizing ESD protection for automotive Ethernet applications
The Top Five Takeaways from the Cybersecurity Panel at the Autonomous Tech Forum 2024
Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
SLM Solutions for Mission-Critical Aerospace and Government Chip Designs
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