Top Story
By combining powerful video engines with a programmable stream unit, the v-MP20x0MOB solution packages are capable of encoding and decoding video up to 720p resolution in a wide range of standards on extremely small silicon area without placing load on the host CPU.
Top Story
The HD-PXL-1.3 transmitter IP core is available in two versions. The first version meets all the current HD (High Definition) standards up to 2.25 Gbps. The second version supports serial communications at a speed of up to 3.5 Gbps per channel for extended HD resolutions, with backward compatibility to the first version of 2.25 Gbps.
Top Story
The DesignWare PHY IP for PCI Express 2.0 includes advanced built-in diagnostic capabilities and ATE test vectors enabling at-speed production testing of the PHY. It is implemented in standard CMOS digital technologies and does not require special process options, providing both ease of integration into a SoC, and ensuring high production yields.
Top Story
The AM 401V offers a fully integrated yet programmable subsystem that is capable of playing back virtually any audio/video content on portable media devices. An industry first, it is optimized to popular audio formats such as AAC, MP3, Dolby Digital and video standards such as MPEG-4, Real Video, VC-1 and H.264 while greatly improving sound fidelity.
Top Story
This multi-protocol SerDes cell provides IBM with a high-performance and low-power solution for implementation on its 45nm silicon-on-insulator (SOI) technology.
Top Story
Architected from the ground up to provide a combination of low-latency, high-performance and low-power options, the Intelli DDR solution incorporates intelligent scheduling algorithms for superior system bandwidth.
Top Story
This solution combines Northwest Logic’s full-featured PCI Express 2.0 Core, DMA Back-End Core, DMA Driver and PCI Express GUI to provide a complete, pre-packaged PCI Express 2.0 solution.
Top Story
Kilopass Technology today announced that its extra-permanent memory (XPM) technology is the first high density embedded NVM technology to complete qualification for 80nm and 90nm process technologies with the successful qualification of its XPM-80GC and XPM-90LP product families.
Top Story
The new SD/SDIO Device HVP is a SD host platform tool based upon Arasan's SD/SDIO host controller used for SDIO device validation. Fully compliant with SD/SDIO v2.0, SD Memory v2.0, and MMC v4.3, the SD socket can interface to any standard SD or MMC card for fast validation.
Top Story
This technology delivers professional picture quality and advanced camera functionality once only found in digital still cameras (DSCs), but now conveniently integrated into mobile phones, portable multimedia players (PMPs), ultra mobile PCs (UMPCs) and security cameras.
Top Story
The latest release includes a new Wake-Up Interrupt (WIC) controller which allows almost instantaneous return to fully active mode from an Ultra-Low Leakage (ULL) retention state and introduces enhanced power management features that address the ongoing need in the embedded market for increased performance and longer battery life in next-generation designs.
Top Story
Gaisler Research today announced that Mentor Graphics Nucleus® Operating System (OS) is now supported on the LEON3 processor.
Top Story
PLDA, the industry leader in the high-speed bus IP market, today announced the immediate availability of their PCIe Gen 2 FPGA IP support for the Virtex®- 5 FXT platform.
Top Story
Barco Silex is pleased to announce its new DCPB-2000 family of JPEG 2000 PCI-Express Acceleration boards. Capitalizing on its leadership in real-time and high-definition JPEG 2000 IP cores, this family of boards encodes and decodes JPEG 2000 in real-time.
Top Story
Alchip Technologies, Inc. and ARM today announced that Alchip has licensed the ARM926EJ-S(TM) processor, Fabric IP and ARM® Physical IP to advance system-on-chip (SoC) design solutions to its customers worldwide
Top Story
In one of the demonstrations for 1394b OHCI Link, Wipro showcased data transfer between an external Hard Disk Drive and a PC along with simultaneous streaming of video from the external hard disk. The PC was connected to Wipro’s PCI based platform running the IEEE 1394b OHCI IP core along with Window’s IEEE 1394 drivers and a 3rd party PHY.
Top Story
coolSRAM-1T™Is Only 65nm SRAM-1T Available in Standard Bulk CMOS process for High-Density Embedded Memory Applications
Top Story
The DesignWare LE IP for PCIe is a cost-effective solution that provides ease-of- use features to simplify the complexities of transitioning to PCI Express for applications requiring a single lane, such as existing PCI/PCI-X designs, ExpressCards, Ethernet controllers, SATA controllers and wireless hubs.
Top Story
Fujitsu Microelectronics America today announced a new collaboration with Prism Circuits to develop a single-lane, variable-data-rate SerDes macro. Built using Fujitsu’s 65-nanometer CS200HP process technology, the macro will be available in the third calendar quarter of 2008.