Design Reuse
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore


Arithmatica, Inc.

Headline       Sign Up for SoC News Alert Publication
  • Arithmatica's Datapath Synthesis Used by Solarflare Communications for New 10GBASE-T PHY Design
  • Jun. 03, 2008
  • Arithmatica Licenses Read Channel Intellectual Property
  • Jan. 21, 2008
  • Arithmatica Releases Major Updates to Datapath Synthesis Tools and Intellectual Property
  • Nov. 20, 2007
  • Arithmatica Appoints New CEO
  • May. 30, 2007
  • Arithmatica Announces Floating Point Library Customer in Advanced 3D Graphics Group
  • May. 24, 2006
  • Arithmatica Updates CellMath Tools for Power Optimization and Tighter Flow Integration for Verilog Users
  • Apr. 05, 2006
  • Arithmatica Expands CellMath Tools Line with CellMath Optimizer for Silicon-Efficient Delivery of Datapath-Oriented Silicon IP
  • Jan. 10, 2006
  • Arithmatica Expands Global Sales Network to Europe to Meet Demand for Efficient Silicon Math in Consumer Electronics ICs
  • Sep. 13, 2005
  • Arithmatica Expands Global Coverage to Meet Demand for Efficient Silicon Math in Consumer Electronics ICs
  • Jun. 13, 2005
  • Arithmatica Enters EDA Market with Proven Tools that Boost Silicon Efficiency by up to 40 Percent for Datapath-Intensive Applications
  • May. 30, 2005
  • Arithmatica IP selected by Xilinx for Virtex-4 XtremeDSP(TM) Slice
  • Mar. 15, 2005
  • Arithmatica Develops Integrated Flow with Cadence Encounter RTL Compiler to Accelerate Design and Verification of Math-Critical Chip
  • Feb. 03, 2005
  • Breakthrough IP from Arithmatica Boosts Silicon Performance, Reduces Chip Area without Changing Design Process
  • Apr. 26, 2004


    Previous Headlines:
    2008JanFebMarAprMayJunJulAugSepOctNov 
    2007JanFebMarAprMayJunJulAugSepOctNovDec
    2006JanFebMarAprMayJunJulAugSepOctNovDec
    2005JanFebMarAprMayJunJulAugSepOctNovDec
    2004JanFebMarAprMayJunJulAugSepOctNovDec
    2003JanFebMarAprMayJunJulAugSepOctNovDec
    2002JanFebMarAprMayJunJulAugSepOctNovDec
    2001JanFebMarAprMayJunJulAugSepOctNovDec
    2000JanFebMarAprMayJunJulAugSepOctNovDec
    1999JanFebMarAprMayJunJulAugSepOctNovDec

    <A HREF="http://www.design-reuse.com/banner/exit.php?id=445" target="_top"><IMG SRC="http://www.us.design-reuse.com/adserver/www/images/eureka_static.jpg" WIDTH=125 HEIGHT=125 BORDER=0></A>